Hagen Sämrow

According to our database1, Hagen Sämrow authored at least 6 papers between 2008 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2012
Effiziente Simulation von Gateoxiddefekten auf Gatterebene mit Transistorlevel-Genauigkeit.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012

Selective redundancy to improve reliability and to slow down delay degradation due to gate oxide breakdown.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Functional enhancements of TMR for power efficient and error resilient ASIC designs.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010
Modeling temperature distribution in Networks-on-Chip using RC-circuits.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009
Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

2008
Encountering gate oxide breakdown with shadow transistors to increase reliability.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008


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