Hafizur Rahaman
Orcid: 0000-0001-9012-5437Affiliations:
- Indian Institute of Engineering Science and Technology, Shibpur, India
- University of Bristol, UK (former)
- Jadavpur University, Kolkata, India (former)
According to our database1,
Hafizur Rahaman
authored at least 294 papers
between 1999 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on iiests.ac.in
-
on orcid.org
On csauthors.net:
Bibliography
2024
An Improved Circuit Transformation Technique for Nearest Neighbor Implementation of Quantum Circuits.
Proceedings of the 28th International Symposium on VLSI Design and Test, 2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
2023
Electrothermal modeling of Multilayer Graphene Nanoribbon (MLGNR) Interconnect considering Energy-per-Layer Screening.
Proceedings of the International Symposium on Devices, Circuits and Systems, 2023
Proceedings of the International Symposium on Devices, Circuits and Systems, 2023
Proceedings of the International Symposium on Devices, Circuits and Systems, 2023
Proceedings of the International Symposium on Devices, Circuits and Systems, 2023
Proceedings of the 13th International Conference on Advances in Information Technology, 2023
Power and Delay Efficient Hardware Implementation with ATPG for Vedic Multiplier Using Urdhva Tiryagbhyam Sutra.
Proceedings of the 13th International Conference on Advances in Information Technology, 2023
2022
MEDA Based Biochips: Detection, Prevention and Rectification Techniques for Cyberphysical Attacks.
IEEE ACM Trans. Comput. Biol. Bioinform., 2022
Microelectron. J., 2022
Frequency-scaled thermal-aware test scheduling for 3D ICs using machine learning based temperature estimation.
Microelectron. J., 2022
J. Circuits Syst. Comput., 2022
Multi-source data fusion technique for parametric fault diagnosis in analog circuits.
Integr., 2022
Hardware Design with Real-Time Implementation for Security of Medical Images and EPMR.
Circuits Syst. Signal Process., 2022
An Online Testing Technique for the Detection of Control Nodes Displacement Faults (CNDF) in Reversible Circuits.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022
Proceedings of the IEEE International Test Conference, 2022
2021
Droplet Transportation in MEDA-Based Biochips: An Enhanced Technique for Intelligent Cross-Contamination Avoidance.
IEEE Trans. Very Large Scale Integr. Syst., 2021
J. Circuits Syst. Comput., 2021
Implementation of Symmetric Functions Using Memristive Nanocrossbar Arrays and their Application in Cryptography.
J. Circuits Syst. Comput., 2021
BDD-based synthesis approach for in-memory logic realization utilizing Memristor Aided loGIC (MAGIC).
Integr., 2021
An improved heuristic technique for nearest neighbor realization of quantum circuits in 2D architecture.
Integr., 2021
Integr., 2021
Binary decision diagram-based synthesis technique for improved mapping of Boolean functions inside memristive crossbar-slices.
IET Comput. Digit. Tech., 2021
Fault-tolerant quantum implementation of conventional decoder logic with enable input.
IET Circuits Devices Syst., 2021
A Statistical Approach of Analog Circuit Fault Detection Utilizing Kolmogorov-Smirnov Test Method.
Circuits Syst. Signal Process., 2021
Simulation-Based Power-Loss Optimization of General-Purpose High-Voltage SiC MOSFET Circuit Under High-Frequency Operation.
IEEE Access, 2021
Neural Network based Indirect Estimation of Functional Parameters of Amplifier by extracting features from Wavelet Transform.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021
A Brief Review of Recent Studies on Performance Improvement of Graphene Nanoribbon Interconnect.
Proceedings of the 4th International Symposium on Devices, Circuits and Systems, 2021
Modelling, Analysis and Optimization of a 4<sup>th</sup> Order Delta-Sigma ADC and its Non-Idealities for Audio Codec Applications Achieving Dynamic Range Above 100dB.
Proceedings of the 4th International Symposium on Devices, Circuits and Systems, 2021
Proceedings of the 4th International Symposium on Devices, Circuits and Systems, 2021
Design of Two-Stage Fully-Differential Driver in SAR ADC with Indirect Feedback Compensation Technique.
Proceedings of the 4th International Symposium on Devices, Circuits and Systems, 2021
Detection of Hardware Trojan in Presence of Sneak Path in Memristive Nanocrossbar Circuits.
Proceedings of the 4th International Symposium on Devices, Circuits and Systems, 2021
2020
Linear Nearest Neighbor Realization of Quantum Circuits Using Clustering and Look-ahead Policy.
J. Circuits Syst. Comput., 2020
IET Comput. Digit. Tech., 2020
Circuits Syst. Signal Process., 2020
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
Efficient Implementation of Nearest Neighbor Quantum Circuits Using Clustering with Genetic Algorithm.
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020
A New Digital Color Image Watermarking Algorithm with its FPGA and ASIC Implementation.
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020
A New Blind Invisible and Semi-Fragile Colour Image Watermarking Scheme in Spatial Domain.
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020
DFT Based Simulation for Predicting Alcohol Adsorption on Oxygenated Functional Group Containing GO and rGO Based Gas Sensor Devices.
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020
An Accelerated Prototype with Movidius Neural Compute Stick for Real-Time Object Detection.
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020
Fault-tolerant Quantum Implementation of Priority Encoder Circuit using Clifford+T-group.
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020
Image Classification Based on Approximate Wavelet Transform and Transfer Learning on Deep Convolutional Neural Networks.
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020
Modeling and Analysis of 3D IC Structures for Heat Mitigation by Thermal Through Silicon Vias.
Proceedings of the 15th IEEE International Conference on Industrial and Information Systems, 2020
Proceedings of the 29th IEEE Asian Test Symposium, 2020
2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
ACM J. Emerg. Technol. Comput. Syst., 2019
Boolean Difference Technique for Detecting All Missing Gate and Stuck-at Faults in Reversible Circuits.
J. Circuits Syst. Comput., 2019
Maximal Defect-Free Component in Nanoscale Crossbar Circuits Amidst Stuck-Open and Stuck-Closed Faults.
J. Circuits Syst. Comput., 2019
A Surface Potential-Based Model for Dual Gate Bilayer Graphene Field Effect Transistor Including the Capacitive Effects.
J. Circuits Syst. Comput., 2019
<i>In</i>-memory designing of Delay and Toggle flip-flops utilizing Memristor Aided loGIC (MAGIC).
Integr., 2019
Int. J. Inf. Syst. Model. Des., 2019
IET Comput. Digit. Tech., 2019
Design and synthesis of improved reversible circuits using AIG- and MIG-based graph data structures.
IET Comput. Digit. Tech., 2019
Boltzmann transport equation-based semi-classical drain current model for bilayer GFET including scattering effects.
IET Circuits Devices Syst., 2019
Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs.
IEICE Trans. Electron., 2019
CoRR, 2019
Dilution with Digital Microfluidic Biochips: How Unbalanced Splits Corrupt Target-Concentration.
CoRR, 2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Improved Look-Ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
Proceedings of the TENCON 2019, 2019
Micro-electrode-dot Array Based Biochips : Advantages of Using Different Shaped CMAs.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019
Efficient Implementation of Fault-Tolerant 4: 1 Quantum Multiplexer (QMUX) Using Clifford+T-Group.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019
Fault-tolerant Quantum Implementation of 1-bit and 4-bit Comparator Circuit using Clifford+T-group.
Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2019
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019
Comparative Stability Analysis of Pristine and AsF5 Intercalation Doped Top Contact Graphene Nano Ribbon Interconnects.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019
Effect of Volumetric Split-Errors on Reactant-Concentration During Sample Preparation with Microfluidic Biochips.
Proceedings of the Advanced Computing and Systems for Security, 2019
2018
A template-based technique for efficient Clifford+T-based quantum circuit implementation.
Microelectron. J., 2018
Synthesis of circuits based on all-optical Mach-Zehnder Interferometers using Binary Decision Diagrams.
Microelectron. J., 2018
FPGA implementation of semi-fragile reversible watermarking by histogram bin shifting in real time.
J. Real Time Image Process., 2018
Analysis of Simultaneous Switching Noise and IR-Drop in Side-Contact Multilayer Graphene Nanoribbon Power Distribution Network.
J. Circuits Syst. Comput., 2018
Homogeneous droplet routing in DMFB: An enhanced technique for high performance bioassay implementation.
Integr., 2018
Improved circuit synthesis approach for exclusive-sum-of-product-based reversible circuits.
IET Comput. Digit. Tech., 2018
Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach.
Circuits Syst. Signal Process., 2018
Computing Fréchet Distance Metric Based L-Shape Tile Decomposition for E-Beam Lithography.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
An Angular Steiner Tree Based Global Routing Algorithm for Graphene Nanoribbon Circuit.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018
A Heuristic Qubit Placement Strategy for Nearest Neighbor Realization in 2D Architecture.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 27th IEEE Asian Test Symposium, 2018
Proceedings of the 27th IEEE Asian Test Symposium, 2018
2017
Analysis of Crosstalk-Induced Effects in Multilayer Graphene Nanoribbon Interconnects.
J. Circuits Syst. Comput., 2017
Hausdorff Distance Driven L-Shape Matching Based Layout Decomposition for E-Beam Lithography.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
Adaptive medical detection system: An iterative averaging method for automated detection analysis using DMFBs.
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017
All optical design of cost efficient multiplier circuit using terahertz optical asymmetric demultiplexer.
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Design of a High-Performance CDMA-Based Broadcast-Free Photonic Multi-Core Network on Chip.
ACM Trans. Embed. Comput. Syst., 2016
Modeling and analysis of crosstalk induced overshoot/undershoot effects in multilayer graphene nanoribbon interconnects and its impact on gate oxide reliability.
Microelectron. Reliab., 2016
Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability.
ACM J. Emerg. Technol. Comput. Syst., 2016
Investigating the Applicability of Graphene Nanoribbon as Signal and Power Interconnects for Nanometer Designs.
J. Circuits Syst. Comput., 2016
Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
Temperature dependent IR-drop and delay analysis in side-contact multilayer graphene nanoribbon based power interconnects.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016
Cross-reference EWOD driving scheme and cross-contamination aware net placement technique for MEDA based DMFBs.
Proceedings of the 2016 International Conference on Advances in Computing, 2016
An automated design of pin-constrained digital microfluidic biochip on MEDA architecture.
Proceedings of the 2016 International Conference on Advances in Computing, 2016
Proceedings of the 2016 International Conference on Advances in Computing, 2016
Proceedings of the 2016 International Conference on Advances in Computing, 2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
ACM Trans. Design Autom. Electr. Syst., 2015
A Post-Synthesis Optimization Technique for Reversible Circuits Exploiting Negative Control Lines.
IEEE Trans. Computers, 2015
Field Programmable Gate Array and System-on-Chip Based Implementation of Discrete Fast Walsh-Hadamard Transform Domain Image Watermarking Architecture for Real-Time Applications.
J. Low Power Electron., 2015
Modeling of Crosstalk Induced Effects in Copper-Based Nanointerconnects: An ABCD Parameter Matrix-Based Approach.
J. Circuits Syst. Comput., 2015
Optimisation of test architecture in three-dimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips.
IET Comput. Digit. Tech., 2015
Comput. Electr. Eng., 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
All Optical Implementation of Mach-Zehnder Interferometer Based Reversible Sequential Counters.
Proceedings of the 28th International Conference on VLSI Design, 2015
A thermal estimation model for 3D IC using liquid cooled microchannels and thermal TSVs.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Improved supply regulation and temperature compensated current reference circuit with low process variations.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
An adaptive feedback based reversible watermarking algorithm using difference expansion.
Proceedings of the 2nd IEEE International Conference on Recent Trends in Information Systems, 2015
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
3D integration in biochips: New proposed architectures for 3D applications in ATDA based digital microfluidic biochips.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Boolean Difference Technique for Detecting All Missing Gate Faults in Reversible Circuits.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
2014
Trans. Comput. Sci., 2014
Improved Cube List Based Cube Pairing Approach for Synthesis of ESOP Based Reversible Logic.
Trans. Comput. Sci., 2014
On the Suitability of Single-Walled Carbon Nanotube Bundle Interconnects for High-Speed and Power-Efficient Applications.
J. Low Power Electron., 2014
ACM J. Emerg. Technol. Comput. Syst., 2014
Comput. Electr. Eng., 2014
An ABCD Parameter Based Modeling and Analysis of Crosstalk Induced Effects in Multiwalled Carbon Nanotube Bundle Interconnects.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
A Novel Wire Planning Technique for Optimum Pin Utilization in Digital Microfluidic Biochips.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
All optical implementation of Mach-Zehnder interferometer based reversible sequential circuit.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
A 45 uW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Impact of Line Resistance Variations on Crosstalk Delay and Noise in Multilayer Graphene Nano Ribbon Interconnects.
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014
Multilevel Homogeneous Detection Analyzer for Medical Diagnostic Application in Digital Microfluidic Biochips.
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014
Design of a Low Complexity and Fast Hardware Architecture for Digital Image Watermarking in FWHT Domain on FPGA.
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014
An ABCD parameter based modeling and analysis of crosstalk induced effects in Multilayer Graphene Nano Ribbon interconnects.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Automated two stage detection and analyzer system in multipartitioned Digital Microfluidic Biochips.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A new technique for layout based functional testing of modules in Digital Microfluidic Biochips.
Proceedings of the 2014 East-West Design & Test Symposium, 2014
Optimizing test time for core-based 3-d integrated circuits by a technique of bi-partitioning.
Proceedings of the 2014 East-West Design & Test Symposium, 2014
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
A layout based customized testing technique for total microfluidic operations in digital microfluidic biochips.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
Digital Design and Pipelined Architecture for Reversible Watermarking Based on Difference Expansion Using FPGA.
Proceedings of the 2014 International Conference on Information Technology, 2014
Generator for Test Set Construction of SMGF in Reversible Circuit by Boolean Difference Method.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
Proceedings of the Applied Computation and Security Systems - ACSS 2014, 2014
2013
Particle Swarm Optimization Based Reversible Circuit Synthesis Using Mixed Control Toffoli Gates.
J. Low Power Electron., 2013
Built-in-self-test technique for diagnosis of delay faults in cluster-based field programmable gate arrays.
IET Comput. Digit. Tech., 2013
Comput. Electr. Eng., 2013
Derivation of test set for detecting multiple missing-gate faults in reversible circuits.
Comput. Electr. Eng., 2013
Comput. Electr. Eng., 2013
A New Method for Route Based Synthesis and Placement in Digital Microfluidic Biochips.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure.
Proceedings of the Reversible Computation - 5th International Conference, 2013
Proceedings of the Reversible Computation - 5th International Conference, 2013
Multi-objective optimization algorithm for efficient pin-constrained droplet routing technique in digital microfluidic biochip.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Impact of Inductance on the Performance of Single Walled Carbon Nanotube Bundle Interconnects.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
An Intelligent Biochip System for Diagnostic Process Flow Based Integration of Combined Detection Analyzer.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
Digital microfluidic system: A new design for heterogeneous sample based integration of multiple DMFBs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 8th International Design and Test Symposium, 2013
Novel designs of digital detection analyzer for intelligent detection and analysis in digital microfluidic biochips.
Proceedings of the 8th International Design and Test Symposium, 2013
Optimizing test architecture of 3D stacked ICs for partial stack/complete stack using hard SoCs.
Proceedings of the 8th International Design and Test Symposium, 2013
Proceedings of the 8th International Design and Test Symposium, 2013
A new customized testing technique using a novel design of droplet motion detector for digital microfluidic Biochip systems.
Proceedings of the International Conference on Advances in Computing, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Proceedings of the East-West Design & Test Symposium, 2013
A new cross contamination aware routing method with intelligent path exploration in digital microfluidic biochips.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
2012
Two-level clustering-based techniques for intelligent droplet routing in digital microfluidic biochips.
Integr., 2012
A Heuristic Method for Co-optimization of Pin Assignment and Droplet Routing in Digital Microfluidic Biochip.
Proceedings of the 25th International Conference on VLSI Design, 2012
Proceedings of the 25th International Conference on VLSI Design, 2012
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
Simulation Study of an Ultra Thin Body Silicon On Insulator Tunnel Field Effect Transistor.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
VLSI Architecture for Spatial Domain Spread Spectrum Image Watermarking Using Gray-Scale Watermark.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
Design of Content Addressable Memory Architecture Using Carbon Nanotube Field Effect Transistors.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
Proceedings of the IEEE 25th International SOC Conference, 2012
Proceedings of the International Workshop on System Level Interconnect Prediction, 2012
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012
A new digital analyzer for optically detected samples in Digital Microfluidic Biochips.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
A New Algorithm for Routing-Aware Net Placement in Cross-Referencing Digital Microfluidic Biochips.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Efficient and Compact Electrical Modeling of Multi Walled Carbon Nanotube Interconnects.
Proceedings of the International Symposium on Electronic System Design, 2012
Proceedings of the International Symposium on Electronic System Design, 2012
Reversible Logic Circuit Synthesis Using Genetic Algorithm and Particle Swarm Optimization.
Proceedings of the International Symposium on Electronic System Design, 2012
Proceedings of the International Symposium on Electronic System Design, 2012
Proceedings of the International Symposium on Electronic System Design, 2012
Diametric Mesh of Tree (DiaMoT) Routing Framework for High Performance NoCs: A Hierarchical Approach.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012
An intelligent compaction technique for pin constrained routing in cross referencing digital microfluidic biochips.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
Proceedings of the 2012 IEEE International Conference on Automation Science and Engineering, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
IET Comput. Digit. Tech., 2011
Test Planning in Digital Microfluidic Biochips Using Efficient Eulerization Techniques.
J. Electron. Test., 2011
Pseudo-Parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for WPAN.
Circuits Syst. Signal Process., 2011
CCABC: Cyclic Cellular Automata Based Clustering For Energy Conservation in Sensor Networks
CoRR, 2011
Comput. Electr. Eng., 2011
Proceedings of the International Conference on Recent Trends in Information Systems, 2011
A Group-Preferential Parallel-Routing Algorithm for Cross-Referencing Digital Microfluidic Biochips.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the International Symposium on Electronic System Design, 2011
Proceedings of the International Symposium on Electronic System Design, 2011
Proceedings of the International Symposium on Electronic System Design, 2011
Ant Colony Optimization Based Droplet Routing Technique in Digital Microfluidic Biochip.
Proceedings of the International Symposium on Electronic System Design, 2011
Derivation of Automatic Test Set for Detection of Missing Gate Faults in Reversible Circuits.
Proceedings of the International Symposium on Electronic System Design, 2011
Runtime Congestion and Crosstalk Aware Router for FPGA Using Jbits3.0 for Partial Reconfigurable Application.
Proceedings of the International Symposium on Electronic System Design, 2011
Proceedings of the International Symposium on Electronic System Design, 2011
Proceedings of the High Performance Architecture and Grid Computing, 2011
Fast high-performance algorithms for multi-pin droplet routing in digital microfluidic biochips.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
A Multi-pin Droplet Routing Algorithm for Digital Microfluidic Biochips.
Proceedings of the BIODEVICES 2011, 2011
Proceedings of the Advanced Computing, Networking and Security - International Conference, 2011
DFDNM: A Distributed Fault Detection and Node Management Scheme for Wireless Sensor Network.
Proceedings of the Advances in Computing and Communications, 2011
2010
Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of GF(2<sup>m</sup>).
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Simplified bit parallel systolic multipliers for special class of galois field (2<sup>m</sup>) with testability.
IET Comput. Digit. Tech., 2010
IET Comput. Digit. Tech., 2010
Comput. J., 2010
Low complexity montgomery multiplication architecture for elliptic curve cryptography over GF(p<sup>m</sup>).
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the IEEE International Conference on Systems, 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Unified Digit Serial Systolic Montgomery Multiplication Architecture for Special Classes of Polynomials over GF(2m).
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
Proceedings of the 13th IEEE International Conference on Computational Science and Engineering, 2010
Testing of Digital Microfluidic Biochips Using Improved Eulerization Techniques and the Chinese Postman Problem.
Proceedings of the 19th IEEE Asian Test Symposium, 2010
Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits.
Proceedings of the 19th IEEE Asian Test Symposium, 2010
Non-preemptive test scheduling for Network-on-Chip(NoC) based systems by reusing NoC as TAM.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
IET Comput. Digit. Tech., 2009
Comput. Electr. Eng., 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
2008
ACM Trans. Design Autom. Electr. Syst., 2008
An Adaptive BIST Design for Detecting Multiple Stuck-Open Faults in a CMOS Complex Cell.
IEEE Trans. Instrum. Meas., 2008
IEEE Trans. Computers, 2008
On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
On Line Testing of Single Feedback Bridging Fault in Cluster Based FPGA by Using Asynchronous Element.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Proceedings of the 2008 International Conference on Information Networking, 2008
Proceedings of the 17th IEEE Asian Test Symposium, 2008
2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m).
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 16th Asian Test Symposium, 2007
2006
MDVM System Concept, Paging Latency and Round-2 Randomized Leader Election Algorithm in SG.
J. Adv. Comput. Intell. Intell. Informatics, 2006
Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability.
J. Electron. Test., 2006
Proceedings of the IEEE International Conference on Systems, 2006
A heuristic method for constructing hexagonal Steiner minimal trees for routing in VLSI.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006
2005
Recent Trends in the Application of Meta-Heuristics to VLSI Layout Design.
Proceedings of the 2nd Indian International Conference on Artificial Intelligence, 2005
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the Applied Computing, Second Asian Applied Computing Conference, 2004
2003
Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
2002
BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Circuits Using Transition Count.
J. Comput. Sci. Technol., 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999