Hafiz Md. Hasan Babu
According to our database1,
Hafiz Md. Hasan Babu
authored at least 67 papers
between 1998 and 2024.
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Bibliography
2024
A comprehensive approach to detecting chemical adulteration in fruits using computer vision, deep learning, and chemical sensors.
Intell. Syst. Appl., 2024
2023
Prevention of shoulder-surfing attacks using shifting condition using digraph substitution rules.
CoRR, 2023
2022
Chi<sup>2</sup>-MI: A hybrid feature selection based machine learning approach in diagnosis of chronic kidney disease.
Intell. Syst. Appl., 2022
BreastMultiNet: A multi-scale feature fusion method using deep neural network to detect breast cancer.
Array, 2022
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
2018
2017
Power efficient optimum design of the Reversible Plessey Logic Block of a field-programmable gate array.
Sustain. Comput. Informatics Syst., 2017
Quantum Inf. Process., 2017
J. Electron. Test., 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
2016
Microelectron. J., 2016
Low-power and area efficient binary coded decimal adder design using a look up table-based field programmable gate array.
IET Circuits Devices Syst., 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Proceedings of the 28th International Conference on VLSI Design, 2015
An Efficient Design of a Reversible Fault Tolerant n -to-2 ^n Sequence Counter Using Nano Meter MOS Transistors.
Proceedings of the Advances in Swarm and Computational Intelligence, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
IET Comput. Digit. Tech., 2014
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
A novel approach to perform reversible addition/subtraction operations using deoxyribonucleic acid.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A Cascading Wavelet-Feed Forward Neural Network Approach for Forecasting Traffic Flow.
Proceedings of the Workshops of the EDBT/ICDT 2014 Joint Conference (EDBT/ICDT 2014), 2014
A compact realization of an n-bit quantum carry skip adder circuit with optimal delay.
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014
2013
Sustain. Comput. Informatics Syst., 2013
Design of a compact reversible fault tolerant field programmable gate array: A novel approach in reversible logic synthesis.
Microelectron. J., 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 13th IEEE International Conference on BioInformatics and BioEngineering, 2013
2012
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
An efficient approach for designing and minimizing reversible programmable logic arrays.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
2011
Proceedings of the 11th IEEE International Conference on Bioinformatics and Bioengineering, 2011
2010
Wrapper/TAM Co-Optimization and constrained Test Scheduling for SOCs Using Rectangle Bin Packing
CoRR, 2010
Wrapper/TAM Co-Optimization and Test Scheduling for SOCs Using Rectangle Bin Packing Considering Diagonal Length of Rectangles
CoRR, 2010
Building Toffoli Network for Reversible Logic Synthesis Based on Swapping Bit Strings
CoRR, 2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
2008
Microelectron. J., 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
2006
J. Syst. Archit., 2006
A New Approach to Synthesize Multiple-Output Functions Using Reversible Programmable Logic Array.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Realization of Digital Fuzzy Operations Using Multi-Valued Fredkin Gates.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006
2005
Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
An Advanced Minimization Technique for Multiple Valued Multiple Output Logic Expressions Using LUT and Realization Using Current Mode CMOS.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
A heuristic approach to synthesize Boolean functions using TANT network.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004
2003
A Technique for Logic Design of Voltage-Mode Pass Transistor Based Multi-Valued Multiple-Output Logic Circuits.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
2000
Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000
1999
Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999
1998
Design of Multiple-Output Networks using Time Domain Multiplexing and Shared Multi-Terminal Multiple-Valued Decision Diagrams.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998