Habib Mehrez
Orcid: 0000-0002-0692-1754
According to our database1,
Habib Mehrez
authored at least 118 papers
between 1995 and 2023.
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Bibliography
2023
Microprocess. Microsystems, February, 2023
2021
J. Electron. Test., 2021
2018
Novel architectural space exploration environment for multi-FPGA based prototyping systems.
Microprocess. Microsystems, 2018
Des. Autom. Embed. Syst., 2018
2017
J. Signal Process. Syst., 2017
Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support.
Turkish J. Electr. Eng. Comput. Sci., 2017
Comparison of direct and switch-based inter-FPGA routing interconnect for multi-FPGA systems.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
On Exploiting Partitioning-Based Placement Approach for Performances Improvement of 3D FPGA.
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017
2016
Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires.
Microprocess. Microsystems, 2016
Proceedings of the 2016 International Symposium on Rapid System Prototyping, 2016
Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016
The effect of interconnect depopulation on FPGA performances in terms of power, area and delay.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016
Design of advanced 2D and 3D FPGAs: Architecture-level exploration and algorithm-level optimization.
Proceedings of the 11th International Design & Test Symposium, 2016
Proceedings of the 11th International Design & Test Symposium, 2016
Proceedings of the Third Workshop on Cryptography and Security in Computing Systems, 2016
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
2015
Lecture Notes in Electrical Engineering 350, Springer, ISBN: 978-3-319-19174-4, 2015
Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA.
IEEE Micro, 2015
H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture.
IET Comput. Digit. Tech., 2015
Signal multiplexing approach to improve inter-FPGA bandwidth of prototyping platform.
Des. Autom. Embed. Syst., 2015
Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
2014
Power grid redundant path contribution in system on chip (SoC) robustness against electromigration.
Microelectron. Reliab., 2014
Microelectron. J., 2014
Microprocess. Microsystems, 2014
Int. J. Reconfigurable Comput., 2014
Int. J. Embed. Syst., 2014
Int. J. Embed. Real Time Commun. Syst., 2014
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
A reference-based specification tool for creating reliable library development specifications.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Future inter-FPGA communication architecture for multi-FPGA based prototyping (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
Performance Comparison between Multi-FPGA Prototyping Platforms: Hardwired Off-the-Shelf, Cabling, and Custom.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014
Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGA.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014
MPSoC architecture for Component Level Parallelism of H.264/AVC intra prediction encoding chain on SoCLib platform.
Proceedings of the 2014 1st International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), 2014
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014
Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014
2013
Microelectron. Reliab., 2013
Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA.
Microelectron. J., 2013
Integr., 2013
Int. J. Reconfigurable Comput., 2013
Int. J. Reconfigurable Comput., 2013
High speed authenticated encryption for slow changing key applications using reconfigurable devices.
Proceedings of the IFIP Wireless Days, 2013
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013
Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA).
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Partitioning constraints and signal routing approach for multi-FPGA prototyping platform.
Proceedings of the 2013 International Symposium on System on Chip, 2013
Proceedings of 2013 International Conference on IC Design & Technology, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013
High performance 3-dimensional heterogeneous tree-based FPGA architectures (HT-FPGA).
Proceedings of the 10th FPGAworld Conference, 2013
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013
Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping Platform.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013
Proceedings of the 10th International Multi-Conferences on Systems, Signals & Devices, 2013
Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
2012
A new heterogeneous tree-based application specific FPGA and its comparison with mesh-based application specific FPGA.
Microprocess. Microsystems, 2012
Design for prototyping of a parameterizable cluster-based Multi-Core System-on-Chip on a multi-FPGA board.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012
Proceedings of the 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2012
2011
ACM Trans. Reconfigurable Technol. Syst., 2011
Int. J. Reconfigurable Comput., 2011
Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011
2010
Proceedings of the 5th International Design and Test Workshop, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010
Proceedings of the Reconfigurable Computing: Architectures, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009
2008
Estimation et optimisation de la consommation dans les SoC utilisant la simulation précise au cycle.
Tech. Sci. Informatiques, 2008
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008
2007
Proceedings of the First International Symposium on Networks-on-Chips, 2007
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007
2006
Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006
2005
Implementation of Scalable Embedded FPGA for SOC.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation.
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005
2004
2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
A floating-point unit using stochastic arithmetic compliant with the IEEE-754 standard.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
2001
A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmetic.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
A family of redundant multipliers dedicated to fast computation for signal processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), 2000
1998
On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard.
IEEE Trans. Very Large Scale Integr. Syst., 1998
1997
Teaching the design of a chip under the Cadence Opus environment using the Alliance cell libraries.
Proceedings of the 1997 IEEE International Conference on Microelectronic Systems Education, 1997
1995
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995