Haakon Dybdahl

According to our database, Haakon Dybdahl authored at least 6 papers between 2006 and 2007.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2007

An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches.

Haakon Dybdahl, Per Stenström, Lasse Natvig

SIGARCH Comput. Archit. News, 2007

An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors.

Haakon Dybdahl, Per Stenström

Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

2006

Destructive-read in embedded DRAM, impact on power consumption.

Haakon Dybdahl, Per Gunnar Kjeldsberg, Marius Grannæs, Lasse Natvig

J. Embed. Comput., 2006

A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors.

Haakon Dybdahl, Per Stenström, Lasse Natvig

Proceedings of the High Performance Computing, 2006

Cache Write-Back Schemes for Embedded Destructive-Read DRAM.

Haakon Dybdahl, Marius Grannæs, Lasse Natvig

Proceedings of the Architecture of Computing Systems, 2006

Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination.

Haakon Dybdahl, Per Stenström

Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006