H. V. Jayashree

According to our database1, H. V. Jayashree authored at least 8 papers between 2013 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
Design Approaches for Resource and Performance Optimization of Reversible BCD Addition and Unified BCD Addition/Subtraction Circuits.
J. Circuits Syst. Comput., 2018

2017
Efficient Circuit Design of Reversible Square.
Trans. Comput. Sci., 2017

Reversible circuit design for GCD computation in cryptography algorithms.
Int. J. Circuit Theory Appl., 2017

Reversible circuit optimization using modified toffoli templates.
Proceedings of the 2017 International Conference on Advances in Computing, 2017

2016
Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier.
J. Supercomput., 2016

2014
Design of Dedicated Reversible Quantum Circuitry for Square Computation.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013
Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder.
Trans. Comput. Sci., 2013

Performance Optimization of Flagged BCD Adder.
Proceedings of the 6th International Conference on Emerging Trends in Engineering and Technology, 2013


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