H. Udayakumar

According to our database, H. Udayakumar authored at least 13 papers between 1999 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2009

An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis.

Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, H. Udayakumar, N. V. Arvind

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Optimization strategies to improve statistical timing.

Parimala Viswanath, Pranav Murthy, Debajit Das, R. Venkatraman, Ajoy Mandal, Arvind Veeravalli, H. Udayakumar

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Clock gating effectiveness metrics: Applications to power optimization.

Jithendra Srinivas, Madhusudan Rao, Sukumar Jairam, H. Udayakumar, Jagdish C. Rao

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008

Memory Power Modeling - A Novel Approach.

Ajit Gupte, Mohit Sharma, Gaurav Varshney, Lakshmikantha Holla, Parvinder Rana, H. Udayakumar

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

An SSO Based Methodology for EM Emission Estimation from SoCs.

Sukumar Jairam, S. M. Stalin, Jean-Yves Oberle, H. Udayakumar

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Clock gating for power optimization in ASIC design cycle theory & practice.

Sukumar Jairam, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, Jagdish C. Rao

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

2006

A Methodology for Switching Activity Based IO Powerpad Optimisation.

Snehashis Roy, Sukumar Jairam, H. Udayakumar

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005

A Methodology for Fast Vector Based Power Supply and Substrate Noise Analyses.

Sankar P. Debnath, Sukumar Jairam, H. Udayakumar

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

2004

Package-silicon co-design - Experiment with an SOC design.

P. R. Suresh, P. K. Sundararajan, Anshuli Goel, H. Udayakumar, C. Srinivasan, Vasudev Sinari, Raghavendrakumar Ravinutala

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2002

Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon.

Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2000

A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores.

Karthikeyan Madathil, Jagdish C. Rao, Subash Chandar G., Amitabh Menon, Avinash K. Gautam, Amit M. Brahme, H. Udayakumar

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999

A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors.

Avinash K. Gautam, Jagdish C. Rao, Rohit Rathi, H. Udayakumar

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology.

Avinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash Chandar G.

Proceedings of the IEEE International Conference On Computer Design, 1999