H. Peter Hofstee
Orcid: 0000-0001-9649-7338Affiliations:
- TU Delft, The Netherlands
- IBM Research Austin, TX, USA
According to our database1,
H. Peter Hofstee
authored at least 87 papers
between 1990 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on tudelft.nl
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on viaf.org
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on orcid.org
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on id.loc.gov
On csauthors.net:
Bibliography
2024
CoRR, 2024
2023
Proceedings of the Joint Proceedings of Workshops at the 49th International Conference on Very Large Data Bases (VLDB 2023), Vancouver, Canada, August 28, 2023
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023
OctoRay: Framework for Scalable FPGA Cluster Acceleration of Python Big Data Applications.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023
2022
ACM Trans. Reconfigurable Technol. Syst., 2022
A Toolchain for Streaming Dataflow Accelerator Designs for Big Data Analytics: Defining an IR for Composable Typed Streaming Dataflow Designs.
CoRR, 2022
Tydi-lang: a language for typed streaming hardware - A manual for future Tydi-lang compiler developers.
CoRR, 2022
Benchmarking Apache Arrow Flight - A wire-speed protocol for data transfer, querying and microservices.
CoRR, 2022
Communication-Efficient Cluster Scalable Genomics Data Processing Using Apache Arrow Flight.
Proceedings of the 21st International Symposium on Parallel and Distributed Computing, 2022
SALoBa: Maximizing Data Locality and Workload Balance for Fast Sequence Alignment on GPUs.
Proceedings of the 2022 IEEE International Parallel and Distributed Processing Symposium, 2022
Proceedings of the 33rd British Machine Vision Conference 2022, 2022
2021
Generating High-Performance FPGA Accelerator Designs for Big Data Analytics with Fletcher and Apache Arrow.
J. Signal Process. Syst., 2021
IEEE Trans. Cloud Comput., 2021
AutoReCon: Neural Architecture Search-based Reconstruction for Data-free Compression.
Proceedings of the Thirtieth International Joint Conference on Artificial Intelligence, 2021
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2021, 2021
2020
J. Signal Process. Syst., 2020
IEEE Micro, 2020
SoFAr: Shortcut-based Fractal Architectures for Binary Convolutional Neural Networks.
CoRR, 2020
Optimizing performance of GATK workflows using Apache Arrow In-Memory data framework.
BMC Genom., 2020
REAF: Reducing Approximation of Channels by Reducing Feature Reuse Within Convolution.
IEEE Access, 2020
ThymesisFlow: A Software-Defined, HW/SW co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Proceedings of the International Conference on Field-Programmable Technology, 2020
2019
Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision Workshops, 2019
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019
Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019
2018
J. Parallel Distributed Comput., 2018
A 64-GB Sort at 28 GB/s on a 4-GPU POWER9 Node for Uniformly-Distributed 16-Byte Records with 8-Byte Keys.
Proceedings of the High Performance Computing, 2018
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018
Proceedings of the 11th IEEE International Conference on Cloud Computing, 2018
2017
Proc. VLDB Endow., 2017
Proceedings of the International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, 2017
SparkGA: A Spark Framework for Cost Effective, Fast and Accurate DNA Analysis at Scale.
Proceedings of the 8th ACM International Conference on Bioinformatics, 2017
2016
IEEE Comput. Archit. Lett., 2016
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016
Auto-tuning Spark Big Data Workloads on POWER8: Prediction-Based Dynamic SMT Threading.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016
Proceedings of the 9th IEEE International Conference on Cloud Computing, 2016
2015
2014
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014
2013
True hardware random number generation implemented in the 32-nm SOI POWER7+ processor.
IBM J. Res. Dev., 2013
2011
Proceedings of the Encyclopedia of Parallel Computing, 2011
2009
Proceedings of the Multicore Processors and Systems, 2009
Proceedings of the Euro-Par 2009, 2009
2008
Proceedings of the International Conference on Computer Graphics and Interactive Techniques, 2008
2007
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI.
IBM J. Res. Dev., 2007
Proceedings of the 2007 IEEE International Conference on Cluster Computing, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor.
IEEE J. Solid State Circuits, 2006
IEEE J. Solid State Circuits, 2006
Invited speakers II - Real-time supercomputing and technology for games and entertainment.
Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 2006
Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
Proceedings of the 28th Communicating Process Architectures Conference, 2005
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
The design methodology and implementation of a first-generation CELL processor: a multi-core SoC.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Inf. Process. Lett., 2001
2000
IBM J. Res. Dev., 2000
Proceedings of the 37th Conference on Design Automation, 2000
1999
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999
1998
IEEE J. Solid State Circuits, 1998
High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
1997
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997
1995
1994
1991
Proceedings of the Research Directions in High-Level Parallel Programming Languages, 1991
1990