H. Nagai

According to our database, H. Nagai authored at least 6 papers between 1986 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Up to 57% Reduction in Effective Resistivity of Word Lines of 3D-NAND Memory by Grain-Size Control, Material Selection, and Seam Removal.

H. Terada, K. Yamaguchi, T. Yokoi, T. Sameshima, K. Suzuki, G. Nakamura, H. Nagai

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2018

Design and Verification of Large-Scale Optical Circuit Switch Using ULCF AWGs for Datacenter Application.

H. Nagai, Yojiro Mori, Hiroshi Hasegawa, Ken-ichi Sato

JOCN, 2018

2000

Risk-sensitive portfolio optimization with partial information.

H. Nagai

Proceedings of the 39th IEEE Conference on Decision and Control, 2000

1998

A Floating Gate MOS Implementation of Resistive Fuse.

Takashi Matsumoto, T. Sawaji, Takeyasu Sakai, H. Nagai

Neural Comput., 1998

1997

Implementing resistive fuse with floating gate MOS transistors.

T. Sawaji, Takeyasu Sakai, H. Nagai, T. Kunishima, Takashi Matsumoto

Proceedings of International Conference on Neural Networks (ICNN'97), 1997

1986

A New String Search Hardware Architecture for VLSI.

K. Takahashi, H. Yamada, H. Nagai, K. Matsumi

Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986