H. Gregor Molter

Orcid: 0000-0002-6896-1591

According to our database1, H. Gregor Molter authored at least 12 papers between 2008 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

Online presence:

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Bibliography

2012
SynDEVS co-design flow: a hardware-, software co-design flow based on the discrete event system specification model of computation.
PhD thesis, 2012

Automated Generation of Embedded Systems Software from Timed DEVS Model of Computation Specifications.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
A novel cryptoprocessor architecture for chained Merkle signature scheme.
Microprocess. Microsystems, 2011

A simple power analysis attack on a McEliece cryptoprocessor.
J. Cryptogr. Eng., 2011

State space optimization within the DEVS model of computation for timing efficiency.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

2010
A Novel Cryptoprocessor Architecture for the McEliece Public-Key Cryptosystem.
IEEE Trans. Computers, 2010

2009
A Timing Attack against Patterson Algorithm in the McEliece PKC.
Proceedings of the Information, Security and Cryptology, 2009

DEVS2VHDL: Automatic transformation of XML-specified DEVS Model of Computation into synthesizable VHDL code.
Proceedings of the Forum on specification and Design Languages, 2009

SC-DEVS: An efficient SystemC extension for the DEVS model of computation.
Proceedings of the Design, Automation and Test in Europe, 2009

A Novel Processor Architecture for McEliece Cryptosystem and FPGA Platforms.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

2008
Side Channels in the McEliece PKC.
Proceedings of the Post-Quantum Cryptography, Second International Workshop, 2008

A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008


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