H. Fatih Ugurdag
Orcid: 0000-0002-6256-0850Affiliations:
- Ozyegin University, Istanbul, Turkey
According to our database1,
H. Fatih Ugurdag
authored at least 54 papers
between 1992 and 2024.
Collaborative distances:
Collaborative distances:
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Online presence:
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on orcid.org
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on ugurdag.com
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Bibliography
2024
X2V: 3D Organ Volume Reconstruction From a Planar X-Ray Image With Neural Implicit Methods.
IEEE Access, 2024
IEEE Access, 2024
2023
An efficient algorithm for disparity map compression based on spatial correlations and its low-cost hardware architecture.
Integr., November, 2023
PyTorch and CEDR: Enabling Deployment of Machine Learning Models on Heterogeneous Computing Systems.
Proceedings of the 20th ACS/IEEE International Conference on Computer Systems and Applications, 2023
2022
HM-Net: A Regression Network for Object Center Detection and Tracking on Wide Area Motion Imagery.
IEEE Access, 2022
Proceedings of the 30th Signal Processing and Communications Applications Conference, 2022
2021
Turkish J. Electr. Eng. Comput. Sci., 2021
2020
Fast Incremental Least Square Pose Estimation for Hardware Implementation with Rolling Shutter Camera.
Proceedings of the 28th Signal Processing and Communications Applications Conference, 2020
Proceedings of the IEEE East-West Design & Test Symposium, 2020
FPGA Implementation of a Low Latency and High SFDR Direct Digital Synthesizer for Resource-Efficient Quantum-Enhanced Communication.
Proceedings of the IEEE East-West Design & Test Symposium, 2020
2019
J. Signal Process. Syst., 2019
Lossless Look-Up Table Compression for Hardware Implementation of Transcendental Functions.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the VLSI-SoC: New Technology Enabler, 2019
Fast and Efficient Implementation of Lightweight Crypto Algorithm PRESENT on FPGA through Processor Instruction Set Extension.
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019
2018
IEEE Des. Test, 2018
Proceedings of the 15th IEEE/ACS International Conference on Computer Systems and Applications, 2018
2017
J. Signal Process. Syst., 2017
Fast Multiplier Generator for FPGAs with LUT based Partial Product Generation and Column/row Compression.
Integr., 2017
Proceedings of the ICT Innovations 2017, 2017
2016
Proceedings of the Computer and Information Sciences - 31st International Symposium, 2016
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016
2015
Proceedings of the 4th International Workshop on Optical Wireless Communications, 2015
An area efficient real time implementation of dual tree complex wavelet transform in field programmable gate arrays.
Proceedings of the 15th IEEE International Conference on Bioinformatics and Bioengineering, 2015
2014
IEEE Trans. Computers, 2014
Proceedings of the 2014 22nd Signal Processing and Communications Applications Conference (SIU), 2014
Combined AES + AEGIS Architectures for High Performance and Lightweight Security Applications.
Proceedings of the ICT Innovations 2014, 2014
2013
Partial bitstream protection for low-cost FPGAs with physical unclonable function, obfuscation, and dynamic partial self reconfiguration.
Comput. Electr. Eng., 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Enabling difference-based dynamic partial self reconfiguration for large differences.
Proceedings of the 8th International Design and Test Symposium, 2013
Achieving modular dynamic partial reconfiguration with a difference-based flow (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013
Proceedings of the East-West Design & Test Symposium, 2013
Proceedings of the East-West Design & Test Symposium, 2013
Proceedings of the 21st IEEE Symposium on Computer Arithmetic, 2013
2012
Microelectron. J., 2012
Proceedings of the 20th Signal Processing and Communications Applications Conference, 2012
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012
2011
Defect-Aware Nanocrossbar Logic Mapping through Matrix Canonization Using Two-Dimensional Radix Sort.
ACM J. Emerg. Technol. Comput. Syst., 2011
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Proceedings of the 9th East-West Design & Test Symposium, 2011
2010
Proceedings of the Computer and Information Sciences, 2010
Proceedings of the 2010 International Conference on High Performance Computing & Simulation, 2010
Defect-aware nanocrossbar logic mapping using Bipartite Subgraph Isomorphism & canonization.
Proceedings of the 15th European Test Symposium, 2010
2006
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006
1996
Autocircuit: a clock edge general behavioral synthesis system with a direct path to physical datapath.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996
1993
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993
1992
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992