H. C. Srinivasaiah

According to our database, H. C. Srinivasaiah authored at least 5 papers between 2002 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of six.

2017

Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications.

M. C. Parameshwara, H. C. Srinivasaiah

J. Circuits Syst. Comput., 2017

2012

Implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAM.

H. C. Srinivasaiah

Proceedings of the 25th International Conference on VLSI Design, 2012

2004

Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment.

H. C. Srinivasaiah, Navakanta Bhat

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003

Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations.

H. C. Srinivasaiah, Navakanta Bhat

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2002

Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay.

H. C. Srinivasaiah, Navakanta Bhat

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002