Gyungsu Byun

According to our database1, Gyungsu Byun authored at least 10 papers between 2011 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2015
Alloy: Parallel-serial memory channel architecture for single-chip heterogeneous processor systems.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2013
Reevaluating the latency claims of 3D stacked memories.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Utilizing RF-I and intelligent scheduling for better throughput/watt in a mobile GPU memory system.
ACM Trans. Archit. Code Optim., 2012

An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling.
IEEE J. Solid State Circuits, 2012

Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Analysis of Noncoherent ASK Modulation-Based RF-Interconnect for Memory Interface.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
A Low-Overhead and Low-Power RF Transceiver for Short-Distance On- and Off-Chip Interconnects.
IEICE Trans. Electron., 2011

An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

The DIMM tree architecture: A high bandwidth and scalable memory system.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011


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