Gyung-Su Byun

According to our database1, Gyung-Su Byun authored at least 17 papers between 2014 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
The Comparison Features of ECG Signal with Different Sampling Frequencies and Filter Methods for Real-Time Measurement.
Symmetry, 2021

A High-speed Wireless Data Transfer for Non - Destructive Testing.
Proceedings of the 18th International SoC Design Conference, 2021

2018
Three-Dimensional Pipeline ADC Utilizing TSV/ Design Optimization and Memristor Ratioed Logic.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Wide-Range Low-Power PLL-Based PI Multiphase Generator Using an Adaptive Frequency Tracking Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Design of a Pre-Distortion Power Amplifier for Ku-Band/5G Applications.
Proceedings of the 2018 IEEE International Conference on Electro/Information Technology, 2018

A 3D flash ADC structure for high-speed communication applications.
Proceedings of the IEEE 8th Annual Computing and Communication Workshop and Conference, 2018

2017
An Energy-Efficient Mobile Memory I/O Interface Using Simultaneous Bidirectional Multilevel Dual-Band Signaling.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Automatic Design and Yield Enhancement of Data Converters.
J. Circuits Syst. Comput., 2017

Yield-aware sizing of pipeline ADC using a multiple-objective evolutionary algorithm.
Int. J. Circuit Theory Appl., 2017

A performance-aware I/O interface for 3D stacked memory systems.
Proceedings of the 8th IEEE Annual Ubiquitous Computing, 2017

Low-power and high-performance 2.4 GHz RF transmitter for biomedical application.
Proceedings of the 8th IEEE Annual Ubiquitous Computing, 2017

A low-power and performance-efficient SAR ADC design.
Proceedings of the International SoC Design Conference, 2017

High-performance RF-interconnect for 3D stacked memory.
Proceedings of the International SoC Design Conference, 2017

2016
A 14.4Gb/s/pin 230fJ/b/pin/mm multi-level RF-interconnect for global network-on-chip communication.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A Low-Power 4-PAM Transceiver Using a Dual-Sampling Technique for Heterogeneous Latency-Sensitive Network-on-Chip.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

2014
Comparative analysis of clock distribution networks for TSV-based 3D IC designs.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

An energy-efficient mobile PAM memory interface for future 3D stacked mobile DRAMs.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014


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