Gyoo-Cheol Hwang
According to our database1,
Gyoo-Cheol Hwang
authored at least 6 papers
between 2011 and 2017.
Collaborative distances:
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Bibliography
2017
A 5.8-Gb/s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface.
IEEE J. Solid State Circuits, 2017
2015
10.4 A 5.8Gb/s adaptive integrating duobinary-based DFE receiver for multi-drop memory interface.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A 3.0 Gb/s clock data recovery circuits based on digital DLL for clock-embedded display interface.
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
Line inversion-based mobile TFT-LCD driver IC with accurate quadruple-gamma-curve correction.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011