Gwan S. Choi
Affiliations:- Texas A&M University, College Station, Texas, USA
According to our database1,
Gwan S. Choi
authored at least 81 papers
between 1989 and 2022.
Collaborative distances:
Collaborative distances:
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Online presence:
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on ece.tamu.edu
On csauthors.net:
Bibliography
2022
Int. J. Circuit Theory Appl., 2022
2021
CVR: A Continuously Variable Rate LDPC Decoder Using Parity Check Extension for Minimum Latency.
J. Signal Process. Syst., 2021
2020
Proceedings of the IEEE International Conference on Image Processing, 2020
2019
2018
SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
2017
The Normalized Singular Value Decomposition of Non-Symmetric Matrices Using Givens fast Rotations.
CoRR, 2017
2016
An Encoding Scheme with Constituent Codes Optimization for Polar Code-Aim to Reduce the Decoding Latency.
CoRR, 2016
An Efficient Partial Sums Generator for Constituent Code based Successive Cancellation Decoding of Polar Codes.
CoRR, 2016
Overlapped list successive cancellation approach for hardware efficient polar code decoder.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
TC: Throughput centric successive cancellation decoder hardware implementation for polar codes.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016
2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
CoRR, 2015
Proceedings of the International Conference on Computing, Networking and Communications, 2015
Proceedings of the International Conference on Computing, Networking and Communications, 2015
Proceedings of the 2015 IEEE Global Communications Conference, 2015
2014
ACM Trans. Design Autom. Electr. Syst., 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
2013
Proceedings of the International Conference on Social Computing, SocialCom 2013, 2013
Proceedings of 2013 International Conference on IC Design & Technology, 2013
2012
Unequal Error Protection Based on DVFS for JSCD in Low-Power Portable Multimedia Systems.
ACM Trans. Embed. Comput. Syst., 2012
Exploiting path diversity for low-latency and high-bandwidth with the dual-path NoC router.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Design space exploration for low-power channel decoder in embedded LDPC-H.264 joint decoding architecture.
Int. J. Inf. Technol. Commun. Convergence, 2011
IEEE Des. Test Comput., 2011
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011
Energy-efficient MIMO detection using unequal error protection for embedded joint decoding system.
Proceedings of the 48th Design Automation Conference, 2011
2010
Low-power baseband processing for wireless multimedia systems using unequal error protection.
Proceedings of the 2010 Wireless Telecommunications Symposium, 2010
Proceedings of the NOCS 2010, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels.
J. Low Power Electron., 2009
Comments on "Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes".
EURASIP J. Embed. Syst., 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Array like runtime reconfigurable MIMO detectors for 802.11n WLAN: a design case study.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Proceedings of the 26th International Conference on Computer Design, 2008
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008
2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of IEEE International Conference on Communications, 2007
Proceedings of IEEE International Conference on Communications, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Information Theoretic Capacity of Long On-chip Interconnects in the Presence of Crosstalk.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Information theoretic approach to address delay and reliability in long on-chip interconnects.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Proceedings of the 43rd Design Automation Conference, 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
2004
Scaleable check node centric architecture for LDPC decoder.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Fast Simulation Technique for LDPC Code Analysis.
Proceedings of the International Conference on Wireless Networks, 2004
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
2001
ECC: Extended Condition Coverage for Design Verification Using Excitation and Observation.
Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001
2000
J. Electron. Test., 2000
IEEE Des. Test Comput., 2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
1999
SIGARCH Comput. Archit. News, 1999
1998
Proceedings of the 3rd IEEE International Symposium on High-Assurance Systems Engineering (HASE '98), 1998
Proceedings of the 3rd IEEE International Symposium on High-Assurance Systems Engineering (HASE '98), 1998
1996
IEEE Trans. Computers, 1996
1994
Proceedings of the Digest of Papers: FTCS/24, 1994
1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
Proceedings of the Digest of Papers: FTCS-23, 1993
Proceedings of the Digest of Papers: FTCS-23, 1993
1992
IEEE Trans. Computers, 1992
1989
FOCUS: an experimental environment for validation of fault-tolerant systems - case study of a jet-engine controller.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989