Guy Bois
Orcid: 0000-0002-7595-9975
According to our database1,
Guy Bois
authored at least 65 papers
between 1988 and 2024.
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Bibliography
2024
Real-Time Spacecraft Pose Estimation Using Mixed-Precision Quantized Neural Network on COTS Reconfigurable MPSoC.
Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024
CoChrono: A Unified Hardware/Software Performance Analysis Tool for SoC-FPGA Codesign.
Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024
2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2019
Sci. Program., 2019
2016
IET Comput. Digit. Tech., 2016
Architectural exploration and implementation of an image processing chain with SpaceStudio<sup>™</sup>.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
Proceedings of the 2016 Symposium on Architectures for Networking and Communications Systems, 2016
2015
Analysis and characterization of data energy tradeoffs: For VLSI architectural agility in C-RAN platforms.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015
2014
Design and Test of Adaptive Computing Fabrics for Scalable and High-Efficiency Cognitive SoC Applications.
Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
2013
Enhanced Precision Analysis for Accuracy-Aware Bit-Width Optimization Using Affine Arithmetic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Reduction methods for adapting optical network on chip topologies to 3D architectures.
Microprocess. Microsystems, 2013
Customised soft processor design: a compromise between architecture description languages and parameterisable processors.
IET Comput. Digit. Tech., 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
2011
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
J. Syst. Archit., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
IP characterization methodology for fast and accurate power consumption estimation at transactional level model.
Proceedings of the 28th International Conference on Computer Design, 2010
2009
High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse.
J. Signal Process. Syst., 2009
Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories.
Trans. High Perform. Embed. Archit. Compil., 2009
J. Aerosp. Comput. Inf. Commun., 2009
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009
2008
Microelectron. J., 2008
Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology.
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008
Acceleration of a 3D target tracking algorithm using an application specific instruction set processor.
Proceedings of the 26th International Conference on Computer Design, 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
2007
Proceedings of the ISoLA 2007, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs.
Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007
Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS support.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006
2005
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005
A Methodology for Hw/Sw Specification and Simulation at Multiple Levels of Abstraction.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
2004
Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004
Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004
A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors.
Proceedings of the 2004 Design, 2004
.NET Framework - A Solution for the Next Generation Tools for System-Level Modeling and Simulation.
Proceedings of the 2004 Design, 2004
2003
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003
Proceedings of the Forum on specification and Design Languages, 2003
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003
Applying Multi-Paradigm and Design Pattern Approaches to Hardware/Software Design and Reuse.
Proceedings of the Patterns and Skeletons for Parallel and Distributed Computing, 2003
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI.
IEEE J. Solid State Circuits, 1999
Development of a high performance TSPC library for implementation of large digital building blocks.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
1998
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998
Self Sorting Radix_2 FFT on FPGA using Parallel Pipelined Distributed Arithmetic Blocks.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998
1997
Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations.
IEEE Trans. Very Large Scale Integr. Syst., 1997
1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
1988