Gustavo Liñán Cembrano

Orcid: 0000-0003-1839-555X

According to our database1, Gustavo Liñán Cembrano authored at least 34 papers between 1998 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
On the Use of Artificial Neural Networks for the Automated High-Level Design of ΣΔ Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2024

Design Automation of Analog and Mixed-Signal Circuits Using Neural Networks - A Tutorial Brief.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

Deep Learning-Based Architecture for RF Frame Detection for CR Applications Using Spectrograms.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Live Demonstration: Using ANNs to Predict the Evolution of Spectrum Occupancy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Live Demonstration: Automated Design of Analog and Mixed-Signal Circuits Using Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2015
Live demonstration: Real-time high dynamic range video acquisition using in-pixel adaptive content-aware tone mapping compression.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2013
A hierarchical vision processing architecture oriented to 3D integration of smart camera chips.
J. Syst. Archit., 2013

2012
CMOS-3D Smart Imager Architectures for Feature Detection.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

A 148dB focal-plane tone-mapping QCIF imager.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Control and acquisition system for a High Dynamic Range CMOS Image Sensor.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A 176×144 148dB adaptive tone-mapping imager.
Proceedings of the Sensors, 2012

2011
Demo: Real-time remote reporting of active regions with Wi-FLIP.
Proceedings of the 2011 Fifth ACM/IEEE International Conference on Distributed Smart Cameras, 2011

Wi-FLIP: A wireless smart camera based on a focal-plane low-power image processor.
Proceedings of the 2011 Fifth ACM/IEEE International Conference on Distributed Smart Cameras, 2011

2010
In-pixel ADC for a vision architecture on CMOS-3D technology.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
Integrated Circuitry to Detect Slippage Inspired by Human Skin and Artificial Retinas.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

APS design alternatives in 0.18μm CMOS image sensor technology.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

A focal plane processor for continuous-time 1-D optical correlation applications.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2007
Focal plane processors & pixel level processing: mimicking natural vision systems to solve image processing problems.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

2006
Locust-inspired vision system on chip architecture for collision detection in automotive applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2004
ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O.
IEEE J. Solid State Circuits, 2004

2003
An Improved Elementary Processing Unit For High-Density CNN-Based Mixed-Signal Microprocessors For Vision.
J. Circuits Syst. Comput., 2003

A modem in CMOS technology for data communication on the low-voltage power line.
Integr., 2003

ACE16k: A 128x128 Focal Plane Analog Processor with Digital I/O.
Int. J. Neural Syst., 2003

Analog weight buffering strategy for CNN chips.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 1000FPS@128×128 vision processor with 8-bit digitized I/O.
Proceedings of the ESSCIRC 2003, 2003

2002
ACE4k: An analog I/O 64×64 visual microprocessor chip with 7-bit analog accuracy.
Int. J. Circuit Theory Appl., 2002

Mismatch-induced tradeoffs and scalability of mixed-signal vision chips.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A processing element architecture for high-density focal plane analog programmable array processors.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
CMOS design of focal plane programmable array processors.
Proceedings of the 9th European Symposium on Artificial Neural Networks, 2001

2000
Implementation of non-linear templates using a decomposition technique by a 0.5 μm CMOS CNN universal chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
A Programmable Imager for Very High Speed Cellular Signal Processing.
J. VLSI Signal Process., 1999

SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips.
Int. J. Circuit Theory Appl., 1999

1998
A 64×64 CNN universal chip with analog and digital I/O.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998


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