Gustavo K. Contreras
According to our database1,
Gustavo K. Contreras
authored at least 11 papers
between 2013 and 2017.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Proceedings of the IEEE International Test Conference, 2017
Security vulnerability analysis of design-for-test exploits for asset protection in SoCs.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning.
Proceedings of the 2016 IEEE International Test Conference, 2016
2015
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
2014
Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014
CSST: Preventing distribution of unlicensed and rejected ICs by untrusted foundry and assembly.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
2013
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013