Gururaj Shamanna

According to our database, Gururaj Shamanna authored at least 4 papers between 2010 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Tutorial 1B: Transistors: Past, present and future.

Gururaj Shamanna, Sao-Jie Chen

Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

2012

Using ECC and redundancy to minimize vmin induced yield loss in 6T SRAM arrays.

Gururaj Shamanna, Raja Gaurav, Y. K. Raghavendra, Percy Marfatia, Bhunesh S. Kshatri

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011

A 32nm Westmere-EX Xeon^® enterprise processor.

Shankar Sawant, Utpal Desai, Gururaj Shamanna, Lokesh Sharma, Mandar Ranade, Anil Agarwal, Sampath Dakshinamurthy, Rajagopal Narayanan

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

Process technology and design parameter impact on SRAM Bit-Cell Sleep effectiveness.

Gururaj Shamanna, Bhunesh S. Kshatri, Raja Gaurav, Y. S. Tew, Percy Marfatia, Y. K. Raghavendra, V. Naik

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010