Gürhan Küçük

Orcid: 0000-0002-3589-5321

According to our database1, Gürhan Küçük authored at least 38 papers between 1997 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
Exploring Machine Learning Approaches for QoS Prediction on SMT Processors.
Proceedings of the 11th International Conference on Future Internet of Things and Cloud, 2024

2021
ShapeShifter: a morphable microprocessor for low power.
Turkish J. Electr. Eng. Comput. Sci., 2021

Dynamic issue queue capping for simultaneous multithreaded processors.
Turkish J. Electr. Eng. Comput. Sci., 2021

2020
Hyperheuristics for explicit resource partitioning in simultaneous multithreadedprocessors.
Turkish J. Electr. Eng. Comput. Sci., 2020

2019
A Fine-grain and scalable set-based cache partitioning through threadclassification.
Turkish J. Electr. Eng. Comput. Sci., 2019

2018
Last level cache partitioning via multiverse thread classification.
Turkish J. Electr. Eng. Comput. Sci., 2018

Dynamic Capping of Physical Register Files in Simultaneous Multi-threading Processors for Performance.
Proceedings of the Computer and Information Sciences - 32nd International Symposium, 2018

Application of Machine Learning Techniques on Prediction of Future Processor Performance.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

2017
Edge computing in the Internet of Things.
Int. J. Distributed Sens. Networks, 2017

2016
Memory Partitioning in the Limit.
Int. J. Parallel Program., 2016

Allocation of last level cache partitions through thread classification with parallel universes.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

2015
A Machine Learning Approach for a Scalable, Energy-Efficient Utility-Based Cache Partitioning.
Proceedings of the High Performance Computing - 30th International Conference, 2015

An experimental VoD server for IPTV.
Proceedings of the 2015 23nd Signal Processing and Communications Applications Conference (SIU), 2015

2014
History-Based Predictive Instruction Window Weighting for SMT Processors.
Proceedings of the Supercomputing - 29th International Conference, 2014

2013
Instruction Scheduling in Microprocessors.
Proceedings of the Automated Scheduling and Planning - From Theory to Practice, 2013

Hyper-Heuristics for Performance Optimization of Simultaneous Multithreaded Processors.
Proceedings of the Information Sciences and Systems 2013, 2013

2009
FireSenseTB: a wireless sensor networks testbed for forest fire detection.
Proceedings of the International Conference on Wireless Communications and Mobile Computing: Connecting the World Wirelessly, 2009

2008
RH+: A Hybrid Localization Algorithm for Wireless Sensor Networks.
IEICE Trans. Commun., 2008

2007
Reducing Energy Consumption of Wireless Sensor Networks through Processor Optimizations.
J. Comput., 2007

2006
Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency.
IEEE Trans. Computers, 2006

Reducing Energy Dissipation of Wireless Sensor Processors Using Silent-Store-Filtering MoteCache.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Power-Aware Processors for Wireless Sensor Networks.
Proceedings of the Computer and Information Sciences, 2006

2004
Energy Efficient Comparators for Superscalar Datapaths.
IEEE Trans. Computers, 2004

Isolating Short-Lived Operands for Energy Reduction.
IEEE Trans. Computers, 2004

Complexity-Effective Reorder Buffer Designs for Superscalar Processors.
IEEE Trans. Computers, 2004

2003
Energy-efficient issue queue design.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Energy Efficient Register Renaming.
Proceedings of the Integrated Circuit and System Design, 2003

Power efficient comparators for long arguments in superscalar processors.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Reducing reorder buffer complexity through selective operand caching.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Distributed Reorder Buffer Schemes for Low Power.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Reducing Datapath Energy through the Isolation of Short-Lived Operands.
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003

2002
Energy-Efficient Design of the Reorder Buffer.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Low-complexity reorder buffer architecture.
Proceedings of the 16th international conference on Supercomputing, 2002

A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors.
Proceedings of the 2002 Design, 2002

2001
Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Energy: efficient instruction dispatch buffer design for superscalar processors.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

1997
MaROS: A Framework for Application Development on Mobile Hosts.
Proceedings of the IASTED International Conference on Parallel and Distributed Systems, 1997


  Loading...