Gurgen Harutunyan
Orcid: 0000-0002-9709-8336
According to our database1,
Gurgen Harutunyan
authored at least 56 papers
between 2005 and 2024.
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Legend:
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On csauthors.net:
Bibliography
2024
IEEE Des. Test, December, 2024
Addressing the Combined Effect of Transistor and Interconnect Aging in SRAM towards Silicon Lifecycle Management.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024
Testing for aging in advanced SRAM: From front end of the line transistors to back end of the line interconnects.
Proceedings of the IEEE International Test Conference, 2024
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024
2023
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
Proceedings of the IEEE International Test Conference, 2023
Proceedings of the IEEE International Test Conference, 2023
Proceedings of the IEEE European Test Symposium, 2023
2022
Innovative Practices Track: What's Next for Automotive: Where and How to Improve Field Test and Enhance SoC Safety.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
An Efficient Test Strategy for Detection of Electromigration Impact in Advanced FinFET Memories.
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the IEEE International Test Conference, 2022
2020
IEEE Trans. Emerg. Top. Comput., 2020
Proceedings of the IEEE International Test Conference, 2020
Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications.
Proceedings of the IEEE International Test Conference, 2020
2019
Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
Proceedings of the IEEE International Test Conference, 2019
2018
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Proceedings of the IEEE International Test Conference, 2018
Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM.
Proceedings of the IEEE International Test Conference, 2018
Proceedings of the IEEE International Test Conference, 2018
Proceedings of the IEEE International Test Conference, 2018
Proceedings of the IEEE International Test Conference, 2018
2017
Proceedings of the IEEE International Test Conference, 2017
Advanced functional safety mechanisms for embedded memories and IPs in automotive SoCs.
Proceedings of the IEEE International Test Conference, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Experimental study on Hamming and Hsiao codes in the context of embedded applications.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017
2016
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Overview study on fault modeling and test methodology development for FinFET-based memories.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015
2014
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Proceedings of the 2014 East-West Design & Test Symposium, 2014
2013
An effective solution for building memory BIST infrastructure based on fault periodicity.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
An efficient fault diagnosis and localization algorithm for Successive-Approximation Analog to Digital Converters.
Proceedings of the East-West Design & Test Symposium, 2013
Proceedings of the East-West Design & Test Symposium, 2013
Proceedings of the East-West Design & Test Symposium, 2013
2012
A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
2011
J. Electron. Test., 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
An efficient March test for detection of all two-operation dynamic faults from subclass Sav.
Proceedings of the 2010 East-West Design & Test Symposium, 2010
2008
An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
2007
J. Electron. Test., 2007
A March-based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
2006
Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
A March-Based Algorithm for Location and Full Diagnosis of All Unlinked Static Faults.
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006
Proceedings of the 11th European Test Symposium, 2006
Minimal March-Based Fault Location Algorithm with Partial Diagnosis for all Static Faults in Random Access Memories.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
2005
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005