Guoyong Shi

Orcid: 0000-0002-8655-3487

According to our database1, Guoyong Shi authored at least 93 papers between 1997 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Multistage Op Amp design space exploration by g m / I D sampling and symbolic design equations.
Int. J. Circuit Theory Appl., March, 2024

Finding the longest delay paths for the array-form multipliers using a genetic algorithm.
Integr., 2024

2023
A Memristor Crossbar-Based Lyapunov Equation Solver.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Automatic generation of macromodels and design equations for application to Op Amp design.
Int. J. Circuit Theory Appl., October, 2023

Multilayer Perceptron-Based Stress Evolution Analysis Under DC Current Stressing for Multisegment Wires.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

DRAGON: Dynamic Recurrent Accelerator for Graph Online Convolution.
ACM Trans. Design Autom. Electr. Syst., January, 2023

Realizable Reduction of Multi-Port RCL Networks by Block Elimination.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

2022
A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits.
ACM Trans. Design Autom. Electr. Syst., 2022

A CMOS rectified linear unit operating in weak inversion for memristive neuromorphic circuits.
Integr., 2022

Multilayer Perceptron Based Stress Evolution Analysis under DC Current Stressing for Multi-segment Wires.
CoRR, 2022

A Supervised Learning Rule for Recurrent Spiking Neural Networks with Weighted Spikes.
Proceedings of the 34th IEEE International Conference on Tools with Artificial Intelligence, 2022

2021
ACE-GCN: A Fast Data-driven FPGA Accelerator for GCN Embedding.
ACM Trans. Reconfigurable Technol. Syst., 2021

High-Dimensional Extension of the TICER Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Sizing of multi-stage Op Amps by combining design equations with the gm/ID method.
Integr., 2021

An analytical gm/ID-based harmonic distortion prediction method for multistage operational amplifiers.
Int. J. Circuit Theory Appl., 2021

Advances in Continuous-time MASH ΔΣ Modulators.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

Design of Analog CMOS-Memristive Neural Network Circuits for Pattern Recognition.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

A Time Constant Estimation Method for Block RC Circuits with Application to Power Grid Analysis.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
Automatic Stage-form Circuit Reduction for Multistage Opamp Design Equation Generation.
ACM Trans. Design Autom. Electr. Syst., 2020

2019
Symbolic Distortion Analysis of Multistage Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A novel design of memristor-based bidirectional associative memory circuits using Verilog-AMS.
Neurocomputing, 2019

Closed-Form Distortion Formulas for Continuous-Time Sigma-Delta Modulators.
IEEE Access, 2019

2018
Generating the Closed-Form Second-Order Characteristics of Analog Differential Cells by Symbolic Perturbation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A fast symbolic SNR computation method and its Verilog-A implementation for Sigma-Delta modulator design optimization.
Integr., 2018

Toward automated reasoning for analog IC design by symbolic computation - A survey.
Integr., 2018

Regression model based consensus for clock synchronisation of wireless sensor network.
Int. J. Sens. Networks, 2018

A Supervised Multi-spike Learning Algorithm for Recurrent Spiking Neural Networks.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2018, 2018

A Circuit Implementation Method for Memristor Crossbar with On-chip Training.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Symbolic Circuit Reduction for Multistage Amplifier Macromodeling.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Topological Approach to Automatic Symbolic Macromodel Generation for Analog Integrated Circuits.
ACM Trans. Design Autom. Electr. Syst., 2017

Topological Approach to Symbolic Pole-Zero Extraction Incorporating Design Knowledge.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

A comparative study on using linear programming and simulated annealing in the optimal realization of a SC filter.
Int. J. Circuit Theory Appl., 2017

Developing a web-based symbolic circuit analysis tool for learning and design aid.
Proceedings of the 14th International Conference on Synthesis, 2017

A current-feedback method for programming memristor array in bidirectional associative memory.
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

2016
GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2016

On the Nonconvergence of the Vector Fitting Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Parallel GMRES solver for fast analysis of large linear dynamic systems on GPU platforms.
Integr., 2016

A high-voltage stimulation chip for wearable stroke rehabilitation systems.
Int. J. Circuit Theory Appl., 2016

An Automatic Integrator Macromodel Generation Method for Behavioral Simulation of SC Sigma-Delta Modulators.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

2015
Two-graph analysis of pathological equivalent networks.
Int. J. Circuit Theory Appl., 2015

H<sup>2</sup>-matrix-based finite element linear solver for fast transient thermal analysis of high-performance ICs.
Int. J. Circuit Theory Appl., 2015

Statistical rare event analysis using smart sampling and parameter guidance.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Optimal realization of switched-capacitor circuits by symbolic analysis.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Rare event diagnosis by iterative failure region locating and elite learning sample selection.
Proceedings of the 16th Latin-American Test Symposium, 2015

A symbolic SC integrator model for fast time-response simulation.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Topological symbolic simplification for analog design.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

An interactive program for automatic network function generation with insights.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A vehicle electric control unit over-the-air reprogramming system.
Proceedings of the International Conference on Connected Vehicles and Expo, 2015

2014
Symbolic computation of SNR for variational analysis of sigma-delta modulator.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Symbolic Moment Computation for Statistical Analysis of Large Interconnect Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Performance bound analysis of analog circuits in frequency- and time-domain considering process variations.
ACM Trans. Design Autom. Electr. Syst., 2013

Graph-Pair Decision Diagram Construction for Topological Symbolic Circuit Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Statistical full-chip total power estimation considering spatially correlated process variations.
Integr., 2013

SRAM dynamic stability verification by reachability analysis with consideration of threshold voltage variation.
Proceedings of the International Symposium on Physical Design, 2013

Stable backward reachability correction for PLL verification with consideration of environmental noise induced jitter.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Incremental symbolic construction for topological modeling of analog circuits.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Passivity Enforcement for Descriptor Systems Via Matrix Pencil Perturbation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Symbolic time-varying root-locus analysis for oscillator design.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

A size sensitivity method for interactive MOS circuit sizing.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Hierarchical graph reduction approach to symbolic circuit analysis with data sharing and cancellation-free properties.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Time-domain performance bound analysis of analog circuits considering process variations.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
An efficient statistical chip-level total power estimation method considering process variations with spatial correlation.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Statistical full-chip dynamic power estimation considering spatial correlations.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Hierarchical symbolic sensitivity computation with applications to large amplifier circuit design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Performance bound analysis of analog circuits considering process variations.
Proceedings of the 48th Design Automation Conference, 2011

Hierarchical exact symbolic analysis of large analog integrated circuits by symbolic stamps.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Battery state of charge estimation using adaptive subspace identification method.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Computational Complexity Analysis of Determinant Decision Diagram.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A simple implementation of determinant decision diagram.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

A fast symbolic computation approach to statistical analysis of mesh networks with multiple sources.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

A design platform for analog device size sensitivity analysis and visualization.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Variational Analog Integrated Circuit Design via Symbolic Sensitivity Analysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
New approaches to interconnect macromodeling with explicit delay extraction.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
A Graph Reduction Approach to Symbolic Circuit Analysis.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

On symbolic model order reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Implementation of a Symbolic Circuit Simulator for Topological Network Analysis.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Model-order reduction by dominant subspace projection: error bound, subspace computation, and circuit applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

2004
Properties of recoverable region and semi-global stabilization in recoverable region for linear systems subject to constraints.
Autom., 2004

Parametric reduced order modeling for interconnect analysis.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Semi-global stabilization of linear systems subject to non-right invertible constraints.
Proceedings of the American Control Conference, 2003

2002
Semi-global stabilization and output regulation of constrained linear plants via measurement feedback.
Proceedings of the 41st IEEE Conference on Decision and Control, 2002

On the input-to-state stability (ISS) of a double integrator with saturated linear control laws.
Proceedings of the American Control Conference, 2002

2001
Constrained output regulation of discrete-time linear plants.
Proceedings of the 40th IEEE Conference on Decision and Control, 2001

Internal stabilization and external L<sub>P</sub> stabilization of linear systems subject to constraints.
Proceedings of the 40th IEEE Conference on Decision and Control, 2001

Constrained stabilization problems for discrete-time linear plants.
Proceedings of the American Control Conference, 2001

2000
Optimal bidirectional associative memories.
Int. J. Syst. Sci., 2000

Generalized output regulation of linear plants with actuators subject to amplitude and rate saturations.
Proceedings of the American Control Conference, 2000

On L<sub>p</sub> (l<sub>p</sub>) performance with global internal stability for linear systems with actuators subject to amplitude and rate saturations.
Proceedings of the American Control Conference, 2000

On optimal output regulation for linear systems-state feedback.
Proceedings of the American Control Conference, 2000

1998
On achieving L p (ℓp) performance with global internal stability for linear plants with saturating actuators.
Proceedings of the Robustness in Identification and Control, Workshop Robustness in Identification and Control, Siena, Italy, July 30, 1998

1997
Genetic approach to the design of bidirectional associative memory.
Int. J. Syst. Sci., 1997

A genetic algorithm applied to a classic job-shop scheduling problem.
Int. J. Syst. Sci., 1997


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