Guoliang Li

According to our database, Guoliang Li authored at least 9 papers between 2012 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Access-Time Minimization for the IJTAG Network Using Data Broadcast and Hardware Parallelism.

Zhanwei Zhong, Guoliang Li, Qinfu Yang, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2018

Broadcast-based minimization of the overall access time for the IEEE 1687 network.

Zhanwei Zhong, Guoliang Li, Qinfu Yang, Jun Qian, Krishnendu Chakrabarty

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism.

Zhanwei Zhong, Guoliang Li, Qinfu Yang, Krishnendu Chakrabarty

Proceedings of the IEEE International Test Conference, 2018

Industrial Case Studies of SoC Test Scheduling Optimization by Selecting Appropriate EDT Architectures.

Guoliang Li, Henry Zhao, Qinfu Yang, Jun Qian, Yu Huang

Proceedings of the IEEE International Test Conference in Asia, 2018

2017

ExTest Scheduling and Optimization for 2.5-D SoCs With Wrapped Tiles.

Ran Wang, Guoliang Li, Rui Li, Jun Qian, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

2015

ExTest scheduling for 2.5D system-on-chip integrated circuits.

Ran Wang, Guoliang Li, Rui Li, Jun Qian, Krishnendu Chakrabarty

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Hybrid Hierarchical and Modular Tests for SoC Designs.

Guoliang Li, Jun Qian, Qinfu Yang, Yuan Zuo, Rui Li, Yu Huang, Mark Kassab, Janusz Rajski

Proceedings of the 24th IEEE North Atlantic Test Workshop, 2015

2013

Scan Test Data Volume Reduction for SoC Designs in EDT Environment.

Guoliang Li, Jun Qian, Yuan Zuo, Rui Li, Qinfu Yang

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Multi-level EDT to Reduce Scan Channels in SoC Designs.

Guoliang Li, Jun Qian, Peter Li, Greg Zuo

Proceedings of the 21st IEEE Asian Test Symposium, 2012