Gunjan Pandya

According to our database, Gunjan Pandya authored at least 5 papers between 2006 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

On-Chip High-Resolution Timing Characterization Circuits for Memory IPs.

Amit Agarwal, Steven Hsu, Mark A. Anders, Gunjan Pandya, Ram Krishnamurthy, James W. Tschanz, Vivek De

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2010

Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process.

Dinesh Somasekhar, Balaji Srinivasan, Gunjan Pandya, Fatih Hamzaoglu, Muhammad M. Khellah, Tanay Karnik, Kevin Zhang

IEEE J. Solid State Circuits, 2010

2009

Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits.

Muhammad M. Khellah, Nam-Sung Kim, Yibin Ye, Dinesh Somasekhar, Tanay Karnik, Nitin Borkar, Gunjan Pandya, Fatih Hamzaoglu, Tom Coan, Yih Wang, Kevin Zhang, Clair Webb, Vivek De

IEEE J. Solid State Circuits, 2009

2007

A 256-Kb Dual-V_CC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.

Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Murad Sunna, James W. Tschanz, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De

IEEE J. Solid State Circuits, 2007

2006

A 4.2GHz 0.3mm2 256kb Dual-V_cc SRAM Building Block in 65nm CMOS.

Muhammad M. Khellah, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Yibin Ye, James W. Tschanz, Dinesh Somasekhar, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006