Gunjan Mandal

According to our database1, Gunjan Mandal authored at least 8 papers between 2004 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020

2011
A 40 nm CMOS 0.4-6 GHz Receiver Resilient to Out-of-Band Blockers.
IEEE J. Solid State Circuits, 2011

A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A 5 mm<sup>2</sup> 40 nm LP CMOS Transceiver for a Software-Defined Radio Platform.
IEEE J. Solid State Circuits, 2010

A 5mm<sup>2</sup> 40nm LP CMOS 0.1-to-3GHz multistandard transceiver.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A sub-3dB NF voltage-sampling front-end with +18dBm IIP3 and +2dBm blocker compression point.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2005
Low-power LVDS receiver for 1.3Gbps physical layer (PHY) interface.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Low power LVDS transmitter with low common mode variation for 1GB/s-per pin operation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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