Gul N. Khan

Orcid: 0000-0003-3169-5952

Affiliations:
  • Toronto Metropolitan University, Canada
  • University of Saskatchewan, Canada (2000 - 2001)
  • Nanyang Technological University, Singapore (1997 - 2000)
  • Imperial College London, UK (PhD 1989)


According to our database1, Gul N. Khan authored at least 62 papers between 1989 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

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Bibliography

2023
GPU Auto-tuning Framework for Optimal Performance and Power Consumption.
Proceedings of the 15th Workshop on General Purpose Processing Using GPU, 2023

2021
An 8-bit digital-to-time converter with pre-skewing and time interpolation.
IET Circuits Devices Syst., 2021

2020
Reconfigurable on-chip interconnection networks for high performance embedded SoC design.
J. Syst. Archit., 2020

Power and Performance Analysis of Deep Neural Networks for Energy-aware Heterogeneous Systems.
Proceedings of the 2020 IEEE International Conference on Systems, Man, and Cybernetics, 2020

2019
Digitally Interpolated Pre-Skewed Delay-Line Digital-to-Time Converter with Minimum Nonlinearity and Latency.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Design Space Exploration of Embedded Applications on Heterogeneous CPU-GPU Platforms.
Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019

Application Specific Reconfigurable SoC Interconnection Network Architecture.
Proceedings of the Architecture of Computing Systems - ARCS 2019, 2019

2018
Multi-Swarm based NoC Configuration and Synthesis.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Flexible Reconfigurable On-chip Networks for Multi-core SoCs.
Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

2017
Application mapping to mesh NoCs using a Tabu-search based swarm optimization.
Microprocess. Microsystems, 2017

Hybrid multi-swarm optimization based NoC synthesis.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Optimal application mapping to 2D-mesh NoCs by using a tabu-based particle swarm methodology.
Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2017

Congestion Aware Routing for On-Chip Communication in NoC Systems.
Proceedings of the Complex, Intelligent, and Software Intensive Systems, 2017

2016
Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Adaptive VC Organization and Arbitration for Efficient NoC Design.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Dynamic virtual channel and index-based arbitration based Network on Chip router architecture.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

2015
Low-cost authentication protocol for passive, computation capable RFID tags.
Wirel. Networks, 2015

Statically adaptive multi FIFO buffer architecture for network on chip.
Microprocess. Microsystems, 2015

Dynamic VC Organization for Efficient NoC Communication.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Index-Based Round-Robin Arbiter for NoC Routers.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014
Power and chip-area aware network-on-chip modeling for system on chip simulation.
Proceedings of the 7th International ICST Conference on Simulation Tools and Techniques, 2014

Efficient Virtual Channel Organization and Congestion Avoidance in Multicore NoC Systems.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing Workshop, 2014

Novel modulo based Aloha anti-collision algorithm for RFID systems.
Proceedings of the IEEE International Conference on RFID, 2014

Packet-based Adaptive Virtual Channel Configuration for NoC Systems.
Proceedings of the 9th International Conference on Future Networks and Communications (FNC'14) / The 11th International Conference on Mobile Systems and Pervasive Computing (MobiSPC'14) / Affiliated Workshops, 2014

Dynamic Virtual Channel Configuration for Efficient Multicore Systems.
Proceedings of the Eighth International Conference on Complex, 2014

2013
High performance NoC synthesis using analytical modeling and simulation with optimal power and minimal IC area.
J. Syst. Archit., 2013

Password based Secure Authentication Methodology for Wireless Sensor Network.
Proceedings of the PECCS 2013, 2013

A novel key management protocol for RFID systems.
Proceedings of the 2013 9th International Wireless Communications and Mobile Computing Conference, 2013

Towards Hardware Realizations of Intelligent Systems: A Cortical Column Approach.
Proceedings of the 42nd International Conference on Parallel Processing, 2013

Secure RFID Authentication Protocol with Key Updating Technique.
Proceedings of the 22nd International Conference on Computer Communication and Networks, 2013

Symmetric key based RFID authentication protocol with a secure key-updating scheme.
Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013

HPAP: A novel authentication scheme for RFID systems.
Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013

Hardware realization of GALS based cortical column systems.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2012
Utilizing multi-bit connections to improve the area efficiency of unidirectional routing resources for routing multi-bit signals on FPGAs.
Microprocess. Microsystems, 2012

Secure authentication scheme for passive C1G2 RFID tags.
Comput. Networks, 2012

Synthesis of NoC Interconnects for Custom MPSoC Architectures.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Synthesis of NoC Interconnects for Multi-core Architectures.
Proceedings of the Sixth International Conference on Complex, 2012

2011
Designing power and performance optimal application-specific Network-on-Chip architectures.
Microprocess. Microsystems, 2011

XTEA Based Secure Authentication Protocol for RFID Systems.
Proceedings of 20th International Conference on Computer Communications and Networks, 2011

Secure Authentication Protocol for RFID Systems.
Proceedings of 20th International Conference on Computer Communications and Networks, 2011

Multi-objective Tabu Search based topology generation technique for application-specific Network-on-Chip architectures.
Proceedings of the Design, Automation and Test in Europe, 2011

XTEA encryption based novel RFID security protocol.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

Flexible simulation and modeling for 2D topology NoC system design.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

2010
A modeling tool for simulating and design of on-chip network systems.
Microprocess. Microsystems, 2010

Power and Performance Tabu Search Based Multicore Network-on-Chip Design.
Proceedings of the 39th International Conference on Parallel Processing, 2010

The effect of multi-bit based connections on the area efficiency of FPGAs utilizing unidirectional routing resources.
Proceedings of the International Conference on Field-Programmable Technology, 2010

2009
Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCs.
IEEE Trans. Very Large Scale Integr. Syst., 2009

A wide dynamic range CMOS image sensor with pulse-frequency-modulation and in-pixel amplification.
Microelectron. J., 2009

Simulation environment for design and verification of Network-on-Chip and multi-core systems.
Proceedings of the 17th Annual Meeting of the IEEE/ACM International Symposium on Modelling, 2009

Codesign of Embedded Systems with Process/Module Level Real-Time Deadlines.
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

Throughput-based network-on-chip topology generation and analysis.
Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009

2008
CAD tool for hardware software co-synthesis of heterogeneous multiple processor embedded architectures.
Des. Autom. Embed. Syst., 2008

2007
Automatic honeycomb lung segmentation in pediatric ct images.
Proceedings of the 9th International Symposium on Signal Processing and Its Applications, 2007

Hardware-Software Cosynthesis of Multiprocessor Embedded Architectures.
Proceedings of the 21st International Conference on Advanced Information Networking and Applications (AINA 2007), 2007

2006
Hardware-Software Co-Synthesis of Heterogeneous Embedded Computer Systems.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2003
Heterogeneous Hardware-Software System Partitioning using Extended Directed Acyclic Graph.
Proceedings of the ISCA 16th International Conference on Parallel and Distributed Computing Systems, 2003

2000
Content Based Indexing and Retrieval in a Digital Library of Arabic Scripts and Calligraphy.
Proceedings of the Research and Advanced Technology for Digital Libraries, 2000

1998
Fault-tolerant architecture for high performance embedded system applications.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1996
Vision based navigation system for an endoscope.
Image Vis. Comput., 1996

1994
RSM - a restricted shared memory architecture for high speed interprocessor communication.
Microprocess. Microsystems, 1994

1992
Extracting contours by perceptual grouping.
Image Vis. Comput., 1992

1989
Machine vision for endoscope control and navigation.
PhD thesis, 1989


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