Guiming Wu

According to our database, Guiming Wu authored at least 25 papers between 2006 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Acceleration of Multi-Body Molecular Dynamics With Customized Parallel Dataflow.

Quan Deng, Qiang Liu, Ming Yuan, Xiaohui Duan, Lin Gan, Jinzhe Yang, Wenlai Zhao, Zhenxiang Zhang, Guiming Wu, Wayne Luk, Haohuan Fu, Guangwen Yang

IEEE Trans. Parallel Distributed Syst., December, 2024

MSMAC: Accelerating Multi-Scalar Multiplication for Zero-Knowledge Proof.

Pengcheng Qiu, Guiming Wu, Tingqiang Chu, Changzheng Wei, Runzhou Luo, Ying Yan, Wei Wang, Hui Zhang

IACR Cryptol. ePrint Arch., 2024

2023

Topgun: An ECC Accelerator for Private Set Intersection.

Guiming Wu, Qianwen He, Jiali Jiang, Zhenxiang Zhang, Yuan Zhao, Yinchao Zou, Jie Zhang, Changzheng Wei, Ying Yan, Hui Zhang

ACM Trans. Reconfigurable Technol. Syst., December, 2023

E-Booster: A Field-Programmable Gate Array-Based Accelerator for Secure Tree Boosting Using Additively Homomorphic Encryption.

Guiming Wu, Qianwen He, Jiali Jiang, Zhenxiang Zhang, Yunfeng Shi, Xin Long, Linquan Jiang, Shuangchen Li, Yuan Xie, Changzheng Wei, Yuan Zhao, Ying Yan, Hui Zhang, Yinchao Zou

IEEE Micro, 2023

2022

A High-Performance Hardware Architecture for ECC Point Multiplication over Curve25519.

Guiming Wu, Qianwen He, Jiali Jiang, Zhenxiang Zhang, Xin Long, Yuan Zhao, Yinchao Zou

Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

2019

FPGA应用于高性能计算的研究现状和未来挑战 (Research Advances and Future Challenges of FPGA-based High Performance Computing).

Xun Jia, Lei Qian, Guiming Wu, Dong Wu, Xianghui Xie

计算机科学, 2019

2017

A High-Performance Accelerator for Floating-Point Matrix Multiplication.

Xun Jia, Guiming Wu, Xianghui Xie

Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

2015

GF(2m)上椭圆曲线标量乘的硬件结构实现 (Hardware Implementation of Scalar Multiplication on Elliptic Curves over GF(2m)).

Guiming Wu, Fang Zheng, Xianghui Xie, Dong Wu, Xinkai Yan

计算机科学, 2015

面向定制结构的稀疏矩阵分块方法 (Sparse Matrix Blocking Method for Custom Architecture).

Guiming Wu, Miao Wang, Xianghui Xie, Yong Dou, Song Guo

计算机科学, 2015

A deeply-pipelined FPGA-based SpMV accelerator with a hardware-friendly storage scheme.

Song Guo, Yong Dou, Yuanwu Lei, Guiming Wu

IEICE Electron. Express, 2015

2013

High-Performance Architecture for the Conjugate Gradient Solver on FPGAs.

Guiming Wu, Xianghui Xie, Yong Dou, Miao Wang

IEEE Trans. Circuits Syst. II Express Briefs, 2013

2012

A High Performance and Memory Efficient LU Decomposer on FPGAs.

Guiming Wu, Yong Dou, Junqing Sun, Gregory D. Peterson

IEEE Trans. Computers, 2012

Parallelizing sparse LU decomposition on FPGAs.

Guiming Wu, Xianghui Xie, Yong Dou, Junqing Sun, Dong Wu, Yuan Li

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2010

A Unified Co-Processor Architecture for Matrix Decomposition.

Yong Dou, Jie Zhou, Guiming Wu, Jingfei Jiang, Yuanwu Lei, Shi-Ce Ni

J. Comput. Sci. Technol., 2010

FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing.

Yong Dou, Yuanwu Lei, Guiming Wu, Song Guo, Jie Zhou, Li Shen

Proceedings of the 24th International Conference on Supercomputing, 2010

Automatic synthesis of processor arrays with local memories on FPGAs.

Guiming Wu, Yong Dou, Miao Wang

Proceedings of the International Conference on Field-Programmable Technology, 2010

High performance and memory efficient implementation of matrix multiplication on FPGAs.

Guiming Wu, Yong Dou, Miao Wang

Proceedings of the International Conference on Field-Programmable Technology, 2010

Blocking LU Decomposition for FPGAs.

Guiming Wu, Yong Dou, Gregory D. Peterson

Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

2009

A coarse-grained reconfigurable computing architecture with loop self-pipelining.

Yong Dou, Guiming Wu, Jinhui Xu, Xingming Zhou

Sci. China Ser. F Inf. Sci., 2009

Exploiting Fine-Grained Pipeline Parallelism for Wavefront Computations on Multicore Platforms.

Guiming Wu, Miao Wang, Yong Dou, Fei Xia

Proceedings of the ICPPW 2009, 2009

A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs.

Guiming Wu, Yong Dou, Yuanwu Lei, Jie Zhou, Miao Wang, Jingfei Jiang

Proceedings of the FCCM 2009, 2009

2008

Computation rotating for data reuse.

Guiming Wu, Jinhui Xu, Yong Dou, Miao Wang

Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008

2007

Instruction Selection for Subword Level Parallelism Optimizations for Application Specific Instruction Processors.

Miao Wang, Guiming Wu, Zhiying Wang

Proceedings of the Parallel and Distributed Processing and Applications, 2007

The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining.

Yong Dou, Jinhui Xu, Guiming Wu

Proceedings of the Reconfigurable Computing: Architectures, 2007

2006

Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining.

Jinhui Xu, Guiming Wu, Yong Dou, Yazhuo Dong

Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006