Guilhem Larrieu

According to our database, Guilhem Larrieu authored at least 9 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation.

Ian O'Connor, Sara Mannaa, Alberto Bosio, Bastien Deveautour, Damien Deleruyelle, Tetiana Obukhova, Cédric Marchand, Jens Trommer, Çigdem Çakirlar, Bruno Neckel Wesling, Thomas Mikolajick, Oskar Baumgartner, Mischa Thesberg, David Pirker, Christoph Lenz, Zlatan Stanojevic, Markus Karner, Guilhem Larrieu, Sylvain Pelloquin, Konstantinous Moustakas, Jonas Müller, Giovanni Ansaloni, Alireza Amirshahi, David Atienza, Jean-Luc Rouas, Leila Ben Letaifa, Georgeta Bordeall, Charles Brazier, Chhandak Mukherjee, Marina Deng, Yifan Wang, Marc François, Houssem Rezgui, Reveil Lucas, Cristell Maneux

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design.

Yifan Wang, Chhandak Mukherjee, Houssem Rezgui, Marina Deng, Cristell Maneux, Sara Mannaa, Ian O'Connor, Jonas Müller, Sylvain Pelloquin, Guilhem Larrieu

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022

Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors.

Lucas Réveil, Chhandak Mukherjee, Cristell Maneux, Marina Deng, François Marc, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu, Arnaud Poittevin, Ian O'Connor, Oskar Baumgartner, David Pirker

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

A Logic Cell Design and routing Methodology Specific to VNWFET.

Arnaud Poittevin, Ian O'Connor, Cédric Marchand, Alberto Bosio, Cristell Maneux, Chhandak Mukherjee, Guilhem Larrieu, Abhishek Kumar

Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

2020

3D logic cells design and results based on Vertical NWFET technology including tied compact model.

C. Mukherjee, Marina Deng, François Marc, Cristell Maneux, Arnaud Poittevin, Ian O'Connor, Sébastien Le Beux, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu

CoRR, 2020

3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model.

Arnaud Poittevin, Chhandak Mukherjee, Ian O'Connor, Cristell Maneux, Guilhem Larrieu, Marina Deng, Sébastien Le Beux, François Marc, Aurélie Lecestre, Cédric Marchand, Abhishek Kumar

Proceedings of the VLSI-SoC: Design Trends, 2020

2018

Pushing the limits of optical information storage using deep learning.

Peter R. Wiecha, Aurélie Lecestre, Nicolas Mallet, Guilhem Larrieu

CoRR, 2018

2017

1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors.

Chhandak Mukherjee, Cristell Maneux, Julien Pezard, Guilhem Larrieu

Proceedings of the 47th European Solid-State Device Research Conference, 2017

2015

Vertical field effect transistor with sub-15nm gate-all-around on Si nanowire array.

Guilhem Larrieu, Y. Guerfi, X. L. Han, N. Clement

Proceedings of the 45th European Solid State Device Research Conference, 2015