Guido Masera

Muhammad Shafique

Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2021

CarSNN: An Efficient Spiking Neural Network for Event-Based Autonomous Cars on the Loihi Neuromorphic Research Processor.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2021

DVS-Attacks: Adversarial Attacks on Dynamic Vision Sensors for Spiking Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2021

2020

An Area-Efficient Variable-Size Fixed-Point DCT Architecture for HEVC Encoding.

[BibT_eX]

[DOI]

Maurizio Masera

IEEE Trans. Circuits Syst. Video Technol., 2020

Low-Complexity Reconfigurable DCT-V Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis.

[BibT_eX]

[DOI]

Sensors, 2020

An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks.

[BibT_eX]

[DOI]

Future Internet, 2020

Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead.

[BibT_eX]

[DOI]

IEEE Access, 2020

A Hardware Implementation for Code-based Post-quantum Asymmetric Cryptography.

[BibT_eX]

[DOI]

Proceedings of the Fourth Italian Conference on Cyber Security, 2020

FasTrCaps: An Integrated Framework for Fast yet Accurate Training of Capsule Networks.

[BibT_eX]

[DOI]

Alberto Marchisio

Beatrice Bussolino

Alessio Colucci

Muhammad Abdullah Hanif

Muhammad Shafique

Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

Q-CapsNets: A Specialized Framework for Quantizing Capsule Networks.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2020

2019

On the Effect of Approximate-Computing in Motion Estimation.

[BibT_eX]

[DOI]

J. Low Power Electron., 2019

LDPC check node implementation using reversible logic.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2019

Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World.

[BibT_eX]

[DOI]

Future Internet, 2019

X-TrainCaps: Accelerated Training of Capsule Nets through Lightweight Software Optimizations.

[BibT_eX]

[DOI]

Alberto Marchisio

Beatrice Bussolino

Alessio Colucci

Muhammad Abdullah Hanif

Muhammad Shafique

CoRR, 2019

VLSI Architectures for the Steerable-Discrete-Cosine-Transform (SDCT).

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019

2018

A Multi-Kernel Multi-Code Polar Decoder Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Efficient Operation Scheduling in Successive-Cancellation-based polar decoders.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

Approximate-Computing Architectures for Motion Estimation in HEVC.

[BibT_eX]

[DOI]

Proceedings of the 2018 New Generation of CAS, 2018

An Optimized Partial-Distortion-Elimination Based Sum-of-Absolute-Differences Architecture for High-Efficiency-Video-Coding.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018

2017

Adaptive Approximated DCT Architectures for HEVC.

[BibT_eX]

[DOI]

Maurizio Masera

IEEE Trans. Circuits Syst. Video Technol., 2017

Analysis of HEVC transform throughput requirements for hardware implementations.

[BibT_eX]

[DOI]

Signal Process. Image Commun., 2017

Odd type DCT/DST for video coding: Relationships and low-complexity implementations.

[BibT_eX]

[DOI]

Maurizio Masera

Williams Richard Garcia Valverde

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Approximate Arai DCT Architecture for HEVC.

[BibT_eX]

[DOI]

Proceedings of the New Generation of CAS, 2017

Low-Power Hardware Accelerator for Sparse Matrix Convolution in Deep Neural Network.

[BibT_eX]

[DOI]

Proceedings of the Advances in Intelligent Information Hiding and Multimedia Signal Processing, 2017

A low power architecture for AER event-processing microcontroller.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016

Automotive Power-Line Communication Channels: Mathematical Characterization and Hardware Emulator.

[BibT_eX]

[DOI]

Mara Concolato

IEEE Trans. Ind. Electron., 2016

FPGA Accelerator of Algebraic Quasi Cyclic LDPC Codes for nand Flash Memories.

[BibT_eX]

[DOI]

IEEE Des. Test, 2016

Comparison between HEVC and Thor based on objective and subjective assessments.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Systems, Signals and Image Processing, 2016

High Level Synthesis based FPGA Implementation of H.264/AVC Sub-Pixel Luma Interpolation Filters.

[BibT_eX]

[DOI]

Proceedings of the 2016 European Modelling Symposium, 2016

2015

Parallel H.264/AVC Fast Rate-Distortion Optimized Motion Estimation by Using a Graphics Processing Unit and Dedicated Hardware.

[BibT_eX]

[DOI]

Muhammad Usman Shahid

IEEE Trans. Circuits Syst. Video Technol., 2015

Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Unequal Error Protection of Memories in LDPC Decoders.

[BibT_eX]

[DOI]

Paolo Montuschi

IEEE Trans. Computers, 2015

Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures.

[BibT_eX]

[DOI]

Integr., 2015

Comments on "Bitwise Log-Likelihood Ratios for Quadrature Amplitude Modulations".

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2015

Reducing the Dissipated Energy in Multi-standard Turbo and LDPC Decoders.

[BibT_eX]

[DOI]

Amer Baghdadi

Circuits Syst. Signal Process., 2015

Complexity and implementation analysis of synthesized view distortion estimation architecture in 3D High Efficiency Video Coding.

[BibT_eX]

[DOI]

Waqar Ahmad

Masoud Shahshahani Amirhossein

Proceedings of the 2015 International Conference on 3D Imaging, 2015

An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding.

[BibT_eX]

[DOI]

Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

2014

VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2014

Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2014

A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Unified turbo/LDPC code decoder architecture for deep-space communications.

[BibT_eX]

[DOI]

IEEE Trans. Aerosp. Electron. Syst., 2014

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced.

[BibT_eX]

[DOI]

IEEE Signal Process. Lett., 2014

Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding.

[BibT_eX]

[DOI]

Amer Baghdadi

IET Commun., 2014

A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2014

Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications.

[BibT_eX]

[DOI]

Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

Molecular transistor circuits: From device model to circuit simulation.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

A novel decoder architecture for error resilient JPEG2000 applications based on MQ arithmetic.

[BibT_eX]

[DOI]

Saeid Nooshabadi

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Improving Network-on-Chip-based Turbo Decoder Architectures.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2013

A 2.63 Mbit/s VLSI Implementation of SISO Arithmetic Decoders for High Performance Joint Source Channel Codes.

[BibT_eX]

[DOI]

Saeid Nooshabadi

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Power Control for Crossbar-Based Input-Queued Switches.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

Analysis on parallel implementations of fixed-complexity sphere decoder.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2013

A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case Study.

[BibT_eX]

[DOI]

Amer Baghdadi

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

VLSI Architecture for Low-Complexity Motion Estimation in H.264 Multiview Video Coding.

[BibT_eX]

[DOI]

Ashfaq Ahmed

Muhammad Usman Shahid

Enrico Magli

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

FPGA accelerator of Quasi cyclic EG-LDPC codes decoder for NAND flash memories.

[BibT_eX]

[DOI]

Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012

Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation.

[BibT_eX]

[DOI]

VLSI Design, 2012

A System View on Iterative MIMO Detection: Dynamic Sphere Detection versus Fixed Effort List Detection.

[BibT_eX]

[DOI]

Christina Gimmler-Dumont

Frank Kienle

VLSI Design, 2012

High Speed Architectures for Finding the First two Maximum/Minimum Values.

[BibT_eX]

[DOI]

Luca Gaetano Amarù

IEEE Trans. Very Large Scale Integr. Syst., 2012

On Practical Implementation and Generalizations of max<sup>*</sup> Operator for Turbo and LDPC Decoders.

[BibT_eX]

[DOI]

Andrea Dario Giancarlo Biroli

Fotios Gioulekas

IEEE Trans. Instrum. Meas., 2012

An LDPC Decoder Architecture for Wireless Sensor Network Applications.

[BibT_eX]

[DOI]

Sensors, 2012

An application specific instruction set processor based implementation for signal detection in multiple antenna systems.

[BibT_eX]

[DOI]

M. Tamagnone

Microprocess. Microsystems, 2012

Efficient VLSI implementation of soft-input soft-output fixed-complexity sphere decoder.

[BibT_eX]

[DOI]

IET Commun., 2012

Non-recursive max<sup>*</sup> operator with reduced implementation complexity for turbo decoding.

[BibT_eX]

[DOI]

Panayiotis Takis Mathiopoulos

IET Commun., 2012

Reducing the memory for iteration-exchanged information and border future metrics in the HomePlug AV turbo decoder implementation.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Turbo Codes and Iterative Information Processing, 2012

FFT implementation using QCA.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A Network-on-Chip-based turbo/LDPC decoder architecture.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

State Metric Compression Techniques for Turbo Decoder Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

On chip interconnects for multiprocessor turbo decoding architectures.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2011

Look-ahead sphere decoding: algorithm and VLSI architecture.

[BibT_eX]

[DOI]

Micaela Troglia Gamba

IET Commun., 2011

Multiplierless Mumford and Shah Functional Implementation.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2011

A Flexible LDPC code decoder with a Network on Chip as underlying interconnect architecture

[BibT_eX]

[DOI]

CoRR, 2011

A Novel Architecture for Scalable, High Throughput, Multi-standard LDPC Decoder.

[BibT_eX]

[DOI]

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods.

[BibT_eX]

[DOI]

Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

Scalable, High Throughput LDPC Decoder for WiMAX (802.16e) Applications.

[BibT_eX]

[DOI]

Muhammad Awais

Ashwani Singh

Proceedings of the Advances in Computing and Communications, 2011

2010

Turbo NOC: A Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2010

Scalable low-complexity B-spline discrete wavelet transform architecture.

[BibT_eX]

[DOI]

Gianluca Piccinini

IET Circuits Devices Syst., 2010

VLSI Architectures for WIMAX Channel Decoders

[BibT_eX]

[DOI]

CoRR, 2010

Thermal Control for Crossbar-Based Input-Queued Switches.

[BibT_eX]

[DOI]

Proceedings of the Global Communications Conference, 2010

A Novel VLSI Architecture of Fixed-Complexity Sphere Decoder.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

ALOE-Based Flexible LDPC Decoder.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

Decoding the Golden Code: A VLSI Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Efficient Implementation Techniques for Maximum Likelihood-Based Error Correction for JPEG2000.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2009

FPGA implementation of time-frequency analysis algorithms for laser welding monitoring.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2009

Vlsi Implementation of WiMAX Convolutional Turbo Code Encoder and Decoder.

[BibT_eX]

[DOI]

Mario Nicola

J. Circuits Syst. Comput., 2009

A new performance evaluation metric for sub-optimal iterative decoders.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2009

On Optimal and Near-Optimal Turbo Decoding Using Generalized max* Operator.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2009

Look-Ahead Sphere Decoding: Algorithm and performance evaluation.

[BibT_eX]

[DOI]

Micaela Troglia Gamba

Proceedings of the 2009 6th International Symposium on Wireless Communication Systems, 2009

A feasible VLSI engine for soft-input-soft-output for joint source channel codes.

[BibT_eX]

[DOI]

Saeid Nooshabadi

Proceedings of the International Conference on Image Processing, 2009

Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

Enabling VLSI Processing Blocks for MIMO-OFDM Communications.

[BibT_eX]

[DOI]

VLSI Design, 2008

A Flexible UMTS-WiMax Turbo Decoder Architecture.

[BibT_eX]

[DOI]

Mario Nicola

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Corrections to "Multiplierless, Folded 9/7-5/3 Wavelet VLSI Architecture" [Sep 07 770-774].

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Design of a VLSI Decoder for Partially Structured LDPC Codes.

[BibT_eX]

[DOI]

Libero Dinoi

Int. J. Digit. Multim. Broadcast., 2008

Hardware design of a low complexity, parallel interleaver for WiMax duo-binary turbo decoding.

[BibT_eX]

[DOI]

Mario Nicola

IEEE Commun. Lett., 2008

Decoding the golden space-time trellis coded modulation.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2008

Error resilient JPEG2000 decoding for wireless applications.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Image Processing, 2008

VLSI implementation of SISO arithmetic decoders for joint source channel coding.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Implementation of a Flexible LDPC Decoder.

[BibT_eX]

[DOI]

Federico Quaglio

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Multiplierless, Folded 9/7- 5/3 Wavelet VLSI Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Real-time implementation of a time-frequency analysis scheme.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Flexible blocks for high throughput serially concatenated convolutional codes.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Beyond 3G wireless communication system prototype.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Hardware architecture for matrix factorization in mimo receivers.

[BibT_eX]

[DOI]

Peter Nilsson

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006

Low-Complexity, Efficient 9/7 Wavelet Filters VLSI Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Mumford and Shah Functional: VLSI Analysis and Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Pattern Anal. Mach. Intell., 2006

Mixed hardware-software testbed for IEEE-802.11n.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Conference on Testbeds & Research Infrastructures for the DEvelopment of NeTworks & COMmunities (TRIDENTCOM 2006), 2006

Error correcting arithmetic coding for JPEG 2000: memory and performance analysis.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Conference on Mobile Multimedia Communications, 2006

Low-Complexity Video Compression Combining Adaptive Multifoveation and Reuse of High-Resolution Information.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Image Processing, 2006

A VLSI Decoder for the Golden code.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Design of Application Specific Processors for the Cached FFT Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

Hardware co-processors for Real-Time and High-Quality H.264/AVC video coding.

[BibT_eX]

[DOI]

Proceedings of the 14th European Signal Processing Conference, 2006

Interconnection framework for high-throughput, flexible LDPC decoders.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

A new approach to compress the configuration information of programmable devices.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

2005

Design and implementation of phase correlation based motion estimator.

[BibT_eX]

[DOI]

Andrea Molino

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Optimized CORDIC core for frequency-domain motion estimation.

[BibT_eX]

[DOI]

Andrea Molino

Proceedings of the 2005 International Conference on Image Processing, 2005

Low-complexity, efficient 9/7 wavelet filters implementation.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Image Processing, 2005

High Performance Channel Model Hardware Emulator for 802.11n.

[BibT_eX]

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

2004

An electromigration and thermal model of power wires for a priori high-level reliability prediction.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Effects of temperature in deep-submicron global interconnect optimization in future technology nodes.

[BibT_eX]

[DOI]

Microelectron. J., 2004

A statistical model for estimating the effect of process variations on crosstalk noise.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004

Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

2003

Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2003

Coupled electro-thermal modeling and optimization of clock networks.

[BibT_eX]

[DOI]

Microelectron. J., 2003

Effects of Temperature in Deep-Submicron Global Interconnect Optimization.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2003

A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2003

Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2002

Architectural strategies for low-power VLSI turbo decoders.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Clock Distribution Network Optimization under Self-Heating and Timing Constraints.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Embedded IWT evaluation in reconfigurable wireless sensor network.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

System architecture for error-resilient, embedded JPEG2000 wireless delivery.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Digital Signal Processing, 2002

Reconfigurable DSP IP for multimedia applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2002

Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2002

2001

Switching Noise Analysis Framework For High Speed Logic Families.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Hierarchical power supply noise evaluation for early power grid design prediction.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

Synthesis of low-leakage PD-SOI circuits with body-biasing.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Reconfigurable coprocessor based JPEG 2000 implementation.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

JPEG 2000: finite precision representation and hardware implications.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

Noise Safety Design Methodologies.

[BibT_eX]

[DOI]

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

A high accuracy-low complexity model for CMOS delays.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A 50 Mbit/s Iterative Turbo-Decoder.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

1999

VLSI architectures for turbo codes.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1999

A global optimization tool for CMOS logic circuits.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

New 2 Gbit/s CMOS I/O pads.

[BibT_eX]

[DOI]

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

A Quantitative Approach to the Design of an Optimized Hardware Interpreter for Java Byte-Code.

[BibT_eX]

Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999

1998

A 500 MHz 2d-DWT VLSI processor.

[BibT_eX]

[DOI]

Proceedings of the 9th European Signal Processing Conference, 1998

1996

A Parametrical Architecture for Reed-Solomon Decoders.

[BibT_eX]

[DOI]

Mariana-Eugenia Petre