Guenole Lallement
Orcid: 0000-0001-5223-6582
According to our database1,
Guenole Lallement
authored at least 8 papers
between 2016 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
2022
CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference.
IEEE J. Solid State Circuits, 2022
2018
A 2.7 pJ/cycle 16 MHz, 0.7 µW Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI.
IEEE J. Solid State Circuits, 2018
Q-Learning-based Adaptive Power Management for IoT System-on-Chips with Embedded Power States.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 140 nW, 32.768 kHz, 1.9 ppm/°C Leakage-Based Digitally Relocked Clock Reference with 0.1 ppm Long-Term Stability in 28nm FD-SOI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
A 0.40pJ/cycle 981 μm<sup>2</sup> voltage scalable digital frequency generator for SoC clocking.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016