Guenole Lallement

Orcid: 0000-0001-5223-6582

According to our database1, Guenole Lallement authored at least 9 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

2016
2017
2018
2019
2020
2021
2022
2023
2024
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Legend:

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In proceedings 
Article 
PhD thesis 
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Other 

Links

On csauthors.net:

Bibliography

2024
Monza: An Energy-Minimal, General-Purpose Dataflow System-on-Chip for the Internet of Things.
IEEE Micro, 2024

2023
Testbench on a Chip: A Yield Test Vehicle for Resistive Memory Devices.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

2022
CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference.
IEEE J. Solid State Circuits, 2022

2018
A 2.7 pJ/cycle 16 MHz, 0.7 µW Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI.
IEEE J. Solid State Circuits, 2018

Q-Learning-based Adaptive Power Management for IoT System-on-Chips with Embedded Power States.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 140 nW, 32.768 kHz, 1.9 ppm/°C Leakage-Based Digitally Relocked Clock Reference with 0.1 ppm Long-Term Stability in 28nm FD-SOI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A 2.7pJ/cycle 16MHz SoC with 4.3nW power-off ARM Cortex-M0+ core in 28nm FD-SOI.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

A 0.40pJ/cycle 981 μm<sup>2</sup> voltage scalable digital frequency generator for SoC clocking.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
Bio-inspired pH sensing using ion sensitive field effect transistors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016


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