Guanhua Yang

According to our database, Guanhua Yang authored at least 7 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A Multichiplet Computing-in-Memory Architecture Exploration Framework Based on Various CIM Devices.

Zhuoyu Dai, Feibin Xiang, Xiangqu Fu, Yifan He, Wenyu Sun, Yongpan Liu, Guanhua Yang, Feng Zhang, Jinshan Yue, Ling Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

Binary-Stochasticity-Enabled Highly Efficient Neuromorphic Deep Learning Achieves Better-than-Software Accuracy.

Yang Li, Wei Wang, Ming Wang, Chunmeng Dou, Zhengyu Ma, Huihui Zhou, Peng Zhang, Nicola Lepri, Xumeng Zhang, Qing Luo, Xiaoxin Xu, Guanhua Yang, Feng Zhang, Ling Li, Daniele Ielmini, Ming Liu

Adv. Intell. Syst., January, 2024

Ge-doped In2O3: First Demonstration of Utlizing Ge as Oxygen Vacancy Consumer to Break the Mobility/Reliability Tradeoff for High Performance Oxide TFTs.

Jiayi Wang, Ziheng Bai, Kuo Zhang, Zhicheng Wu, Di Geng, Yang Xu, Nannan You, Yuxuan Li, Guanhua Yang, Ling Li, Shengkai Wang, Ming Liu

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

First Demonstration of Monolithic Three-Dimensional Integration of Ultra-High Density Hybrid IGZO/Si SRAM and IGZO 2T0C DRAM Achieving Record-Low Latency (5000s).

Menggan Liu, Zhi Li, Wendong Lu, Kaifei Chen, Jiebin Niu, Fuxi Liao, Zijing Wu, Congyan Lu, Weizeng Li, Di Geng, Nianduan Lu, Chunmeng Dou, Guanhua Yang, Ling Li, Ming Liu

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

IG-CRM: Area/Energy-Efficient IGZO-Based Circuits and Architecture Design for Reconfigurable CIM/CAM Applications.

Zeyu Guo, Jinshan Yue, Shengzhe Yan, Zhuoyu Dai, Xiangqu Fu, Zhaori Cong, Zening Niu, Ke Hu, Lihua Xu, Jiawei Wang, Lingfei Wang, Guanhua Yang, Di Geng, Ling Li

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2022

Vertical Channel-All-Around (CAA) IGZO FET under 50 nm CD with High Read Current of 32.8 μA/μm (Vth + 1 V), Well-performed Thermal Stability up to 120 ℃ for Low Latency, High-density 2T0C 3D DRAM Application.

Kailiang Huang, Xinlv Duan, Junxiao Feng, Ying Sun, Congyan Lu, Chuanke Chen, Guangfan Jiao, Xinpeng Lin, Jinhai Shao, Shihui Yin, Jiazhen Sheng, Zhaogui Wang, Wenqiang Zhang, Xichen Chuai, Jiebin Niu, Wenwu Wang, Ying Wu, Weiliang Jing, Zhengbo Wang, Jeffrey Xu, Guanhua Yang, Di Geng, Ling Li, Ming Liu

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Scaling Dual-Gate Ultra-thin a-IGZO FET to 30 nm Channel Length with Record-high Gm, max of 559 µS/µm at VDS=1 V, Record-low DIBL of 10 mV/V and Nearly Ideal SS of 63 mV/dec.

Kaifei Chen, Jiebin Niu, Guanhua Yang, Menggan Liu, Wendong Lu, Fuxi Liao, Kailiang Huang, XinLv Duan, Congyan Lu, Jiawei Wang, Lingfei Wang, Mengmeng Li, Di Geng, Chao Zhao, Guilei Wang, Nianduan Lu, Ling Li, Ming Liu

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022