Guangyi Lu
Orcid: 0000-0003-1978-4485Affiliations:
- Peking University, Beijing, China
According to our database1,
Guangyi Lu
authored at least 17 papers
between 2013 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Microwave Network-Assisted Analysis and Machine Learning-Assisted Synthesis of Arbitrarily Tapped Coils and Its Application to On-Chip Ultrawideband ESD Protection Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024
2023
Highly Efficient Automatic Synthesis of a Millimeter-Wave On-Chip Deformable Spiral Inductor Using a Hybrid Knowledge-Guided and Data-Driven Technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
2020
A New Behavioral Model of Gate-Grounded NMOS for Simulating Snapback Characteristics.
IEEE Access, 2020
2018
Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness.
IEICE Trans. Electron., 2017
IEICE Electron. Express, 2017
Power-rail ESD clamp circuit with hybrid-detection enhanced triggering in a 65-nm, 1.2-V CMOS process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process.
IEICE Trans. Electron., 2016
IEICE Electron. Express, 2016
Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process.
Sci. China Inf. Sci., 2016
Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process.
Sci. China Inf. Sci., 2016
Sci. China Inf. Sci., 2016
A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling.
Sci. China Inf. Sci., 2015
Four-bit transient-to-digital converter with a single RC-based detection circuit for system-level ESD protection.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2013
Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits.
Proceedings of the IEEE 10th International Conference on ASIC, 2013