Guanghua Shu

According to our database, Guanghua Shu authored at least 22 papers between 2010 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

An Embedding-Based Grocery Search Model at Instacart.

Yuqing Xie, Taesik Na, Xiao Xiao, Saurav Manchanda, Young Rao, Zhihong Xu, Guanghua Shu, Esther Vasiete, Tejaswi Tenneti, Haixun Wang

CoRR, 2022

2018

A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects.

Da Wei, Tejasvi Anand, Guanghua Shu, José E. Schutt-Ainé, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2018

Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers.

Ahmed Elkholy, Saurabh Saxena, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2018

A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation.

Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2018

A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS.

Mostafa Gamal Ahmed, Mrunmay Talegaonkar, Ahmed Elkholy, Guanghua Shu, Ahmed Elmallah, Alexander V. Rylyakov, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2018

Design Considerations of Monolithically Integrated Voltage Regulators for Multicore Processors.

Hesam Fathi Moghadam, Jieun Jang, Michael Dayringer, Thipok Rak-amnouykit, Guanghua Shu, Anatoly Yakovlev, Yue Zhang, David Hopkins

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

A 0.0021 mm² 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS.

Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2017

A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver.

Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2017

A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS.

Junheng Zhu, Makrand Mahalley, Guanghua Shu, Woo-Seok Choi, Romesh Kumar Nandwana, Ahmed Elkholy, Bibhudatta Sahoo, Pavan Kumar Hanumolu

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 0.7V time-based inductor for fully integrated low bandwidth filter applications.

Braedon Salz, Mrunmay Talegaonkar, Guanghua Shu, Ahmed Elmallah, Romesh Kumar Nandwana, Bibhudatta Sahoo, Pavan Kumar Hanumolu

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

Energy-efficient wireline transceivers

Guanghua Shu

PhD thesis, 2016

A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition.

Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2016

19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS.

Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS.

Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Romesh Kumar Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links.

Woo-Seok Choi, Tejasvi Anand, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2015

A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS.

Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Seong Joong Kim, Woo-Seok Choi, Pavan Kumar Hanumolu

Proceedings of the Symposium on VLSI Circuits, 2015

3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS.

Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop.

Guanghua Shu, Saurabh Saxena, Woo-Seok Choi, Mrunmay Talegaonkar, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2014

8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS.

Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Tejasvi Anand, Amr Elshazly, Pavan Kumar Hanumolu

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS.

Ahmed Elkholy, Amr Elshazly, Saurabh Saxena, Guanghua Shu, Pavan Kumar Hanumolu

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2011

A 12-bit 50-MSPS SHA-less opamp-sharing Analog-to-Digital converter in 65nm CMOS.

Chen Shu, Guanghua Shu, Jun Xu, Fan Ye, Junyan Ren

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

A 0.22 pJ/step subsampling ADC with fast input-tracking sampling and simplified opamp sharing.

Guanghua Shu, Fan Ye, Yao Guo, Mingjun Fan, Junyan Ren, Jun Xu, Ning Li, Cheng Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010