Guang-Kaai Dehng

According to our database1, Guang-Kaai Dehng authored at least 19 papers between 1998 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020


2019
An LTE-A Multimode Multiband RF Transceiver with 4RX/2TX Inter-Band Carrier Aggregation, 2-Carrier 4×4 MIMO with 256QAM and HPUE Capability in 28nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2017
13.1 A fully integrated multimode front-end module for GSM/EDGE/TD-SCDMA/TD-LTE applications using a Class-F CMOS power amplifier.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Session 13 overview: High-performance transmitters.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017


2016
Session 9 overview: High-performance wireless.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014
20.7 A multi-band inductor-less SAW-less 2G/3G-TD-SCDMA cellular receiver in 40nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A 65-nm GSM/GPRS/EDGE SoC With Integrated BT/FM.
IEEE J. Solid State Circuits, 2013

A 0.27mm<sup>2</sup> 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
An Ultra-Low-Cost High-Performance Bluetooth SoC in 0.11-µm CMOS.
IEEE J. Solid State Circuits, 2012


2011
An ultra-low-cost Bluetooth SOC in 0.11-μm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A 1.22/6.7 ppm/°C VCO with frequency-drifting compensator in 60 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2009
A 0.13 µm CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture.
IEEE J. Solid State Circuits, 2009

2001
A fast-lock mixed-mode DLL using a 2-b SAR algorithm.
IEEE J. Solid State Circuits, 2001

2000
A 900-MHz 1-V CMOS frequency synthesizer.
IEEE J. Solid State Circuits, 2000

Clock-deskew buffer using a SAR-controlled delay-locked loop.
IEEE J. Solid State Circuits, 2000

1998
New dynamic flip-flops for high-speed dual-modulus prescaler.
IEEE J. Solid State Circuits, 1998


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