Guan-Ying Huang

According to our database1, Guan-Ying Huang authored at least 19 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
Industrial federated learning algorithm (P-PFedSGD) for tool wear estimation.
Future Gener. Comput. Syst., 2024

2021
Federated Learning Architecture for Bearing Fault Diagnosis.
Proceedings of the International Conference on System Science and Engineering, 2021

2014
Low power pipelined SAR ADC with loading-free architecture.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 10b 100kS/s SAR ADC with charge recycling switching method.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
10-bit 30-MS/s SAR ADC Using a Switchback Switching Method.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A successive approximation ADC with resistor-capacitor hybrid structure.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

2012
A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications.
IEEE J. Solid State Circuits, 2012

A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

A power-efficient sizing methodology of SAR ADCs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A pipelined SAR ADC with loading-separating technique in 90-nm CMOS technology.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
Building a Multi-kernel Embedded System with High Performance IPC Mechanism.
Proceedings of the 13th IEEE International Conference on High Performance Computing & Communication, 2011

A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure.
IEEE J. Solid State Circuits, 2010

Building Multi-kernel Embedded System on PAC Multi-core Platform.
Proceedings of the 10th International Conference on Quality Software, 2010

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009


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