Guadalupe Miñana

According to our database, Guadalupe Miñana authored at least 8 papers between 2005 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Enhancing Students' Learning Process Through Self-Generated Tests.

Marcos Sánchez-Élez, Inmaculada Pardines, Pablo García, Guadalupe Miñana, Sara Román Navarro, Margarita Sánchez, José L. Risco-Martín

CoRR, 2024

2013

Memories in Complutense Campus.

Victoria López, Matilde Santos Peñas, Guadalupe Miñana, Raquel Caro, Susanne Escobar-Torres Kraemmer, M. Sánchez Balmaseda, Guillermo Botella Juan

Proceedings of the A Tribute to Prof. Dr. Da Ruan, 2013

2007

Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders.

Guadalupe Miñana, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar, Oscar Garnica, Sonia López

IET Comput. Digit. Tech., 2007

2006

A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors.

Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions.

José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López

Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006

A Power-Aware Technique for Functional Units in High-Performance Processors.

Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart.

José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005

Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width.

Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar

Proceedings of the Integrated Circuit and System Design, 2005