Grzegorz Mrugalski

According to our database, Grzegorz Mrugalski authored at least 65 papers between 1999 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

X-Masking for Deterministic In-System Tests.

Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

2022

LBIST for Automotive ICs With Enhanced Test Generation.

Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

DIST: Deterministic In-System Test with X-masking.

Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak

Proceedings of the IEEE International Test Conference, 2022

X-Masking for In-System Deterministic Test.

Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak

Proceedings of the IEEE European Test Symposium, 2022

2021

X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan.

Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak

IEEE Trans. Very Large Scale Integr. Syst., 2021

Autonomous Scan Patterns for Laser Voltage Imaging.

Wu-Tung Cheng, Sylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer

IEEE Trans. Emerg. Top. Comput., 2021

2020

Scan Integrity Tests for EDT Compression.

Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer

IEEE Des. Test, 2020

X-Tolerant Tunable Compactor for In-System Test.

Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wldarczak

Proceedings of the IEEE International Test Conference, 2020

Test Sequence-Optimized BIST for Automotive Applications.

Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer

Proceedings of the IEEE European Test Symposium, 2020

Scan Chain Diagnosis-Driven Test Response Compactor.

Jakub Janicki, Grzegorz Mrugalski, Artur Stelmach, Szczepan Urban

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

On Cyclic Scan Integrity Tests for EDT-based Compression.

Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

2017

Trimodal Scan-Based Test Paradigm.

Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Chen Wang

IEEE Trans. Very Large Scale Integr. Syst., 2017

Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns.

Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

2015

Low-Power Programmable PRPG With Test Compression Capabilities.

Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer

IEEE Trans. Very Large Scale Integr. Syst., 2015

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures.

Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Very Large Scale Integr. Syst., 2015

A deterministic BIST scheme based on EDT-compressed test patterns.

Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer

Proceedings of the 2015 IEEE International Test Conference, 2015

TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm.

Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Chen Wang

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs".

Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

On Using Implied Values in EDT-based Test Compression.

Marcin Gebala, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs.

Maciej Trawka, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jakub Janicki, Jerzy Tyszer

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Low Power Test Compression with Programmable Broadcast-Based Control.

Sylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Test Time Reduction in EDT Bandwidth Management for SoC Designs.

Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

On Deploying Scan Chains for Data Storage in Test Compression Environment.

Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer

IEEE Des. Test, 2013

New test compression scheme based on low power BIST.

Jerzy Tyszer, Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski

Proceedings of the 18th IEEE European Test Symposium, 2013

2012

EDT Bandwidth Management in SoC Designs.

Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Test generator with preselected toggling for low power built-in self-test.

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Low power programmable PRPG with enhanced fault coverage gradient.

Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski

Proceedings of the 2012 IEEE International Test Conference, 2012

Bandwidth-aware test compression logic for SoC designs.

Jakub Janicki, Jerzy Tyszer, Grzegorz Mrugalski, Janusz Rajski

Proceedings of the 17th IEEE European Test Symposium, 2012

2011

Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression.

Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs.

Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer

J. Electron. Test., 2011

Ring Generator: An Ultimate Linear Feedback Shift Register.

Nilanjan Mukherjee, Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer

Computer, 2011

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism.

Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski

Proceedings of the 2011 IEEE International Test Conference, 2011

Reduced ATE Interface for High Test Data Compression.

Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer

Proceedings of the 16th European Test Symposium, 2011

Diagnosis of Failing Scan Cells through Orthogonal Response Compaction.

Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer

Proceedings of the 16th European Test Symposium, 2011

Fault Diagnosis in Memory BIST Environment with Non-march Tests.

Grzegorz Mrugalski, Artur Pogiel, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Pawel Urbanek

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Low Power Decompressor and PRPG with Constant Value Broadcast.

Michal Filipek, Yoshiaki Fukui, Hiroyuki Iwata, Grzegorz Mrugalski, Janusz Rajski, Masahiro Takakura, Jerzy Tyszer

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

On Compaction Utilizing Inter and Intra-Correlation of Unknown States.

Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Dynamic channel allocation for higher EDT compression in SoC designs.

Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer

Proceedings of the 2011 IEEE International Test Conference, 2010

Low power compression of incompatible test cubes.

Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer

Proceedings of the 2011 IEEE International Test Conference, 2010

2009

Low-Power Scan Operation in Test Compression Environment.

Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Highly X-Tolerant Selective Compaction of Test Responses.

Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Compression based on deterministic vector clustering of incompatible test cubes.

Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer

Proceedings of the 2009 IEEE International Test Conference, 2009

2008

X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector.

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Low-Power Test Data Application in EDT Environment Through Decompressor Freeze.

Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Low Power Scan Shift and Capture in the EDT Environment.

Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer

Proceedings of the 2008 IEEE International Test Conference, 2008

2007

Fault Diagnosis With Convolutional Compactors.

Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Isolation of Failing Scan Cells through Convolutional Test Response Compaction.

Grzegorz Mrugalski, Janusz Rajski, Chen Wang, Artur Pogiel, Jerzy Tyszer

J. Electron. Test., 2007

X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis.

Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai

IEEE Des. Test Comput., 2007

Low Power Embedded Deterministic Test.

Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

New Test Data Decompressor for Low Power Applications.

Grzegorz Mrugalski, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer

Proceedings of the 44th Design Automation Conference, 2007

2006

High Performance Dense Ring Generators.

Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Computers, 2006

X-Press Compactor for 1000x Reduction of Test Data.

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab

Proceedings of the 2006 IEEE International Test Conference, 2006

Test response compactor with programmable selector.

Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer

Proceedings of the 43rd Design Automation Conference, 2006

2005

Diagnosis with convolutional compactors in presence of unknown states.

Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Convolutional compaction-driven diagnosis of scan failures.

Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer, Chen Wang

Proceedings of the 10th European Test Symposium, 2005

2004

Ring generators - new devices for embedded test applications.

Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Planar High Performance Ring Generators.

Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Fault Diagnosis in Designs with Convolutional Compactors.

Grzegorz Mrugalski, Chen Wang, Artur Pogiel, Jerzy Tyszer, Janusz Rajski

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

2D Test Sequence Generators.

Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski

IEEE Des. Test Comput., 2003

High Speed Ring Generators and Compactors of Test Data.

Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

2002

Embedded Deterministic Test for Low-Cost Manufacturing Test.

Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2000

Cellular automata-based test pattern generators with phase shifters.

Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators.

Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

1999

Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters.

Janusz Rajski, Grzegorz Mrugalski, Jerzy Tyszer

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Synthesis of pattern generators based on cellular automata with phase shifters.

Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999