Grzegorz Borowik
Orcid: 0000-0003-4148-4817
According to our database1,
Grzegorz Borowik
authored at least 24 papers
between 2007 and 2023.
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Bibliography
2023
Expert Syst. Appl., November, 2023
Numer. Algorithms, July, 2023
2022
Proceedings of the Computer Aided Systems Theory - EUROCAST 2022, 2022
2021
Proceedings of the 19th International Conference on Information Technology Based Higher Education and Training, 2021
2020
Comparison of algorithms for dimensionality reduction and their application to index generation functions.
Proceedings of the 15th IEEE International Conference of System of Systems Engineering, 2020
2018
Optimization on the Complementation Procedure Towards Efficient Implementation of the Index Generation Function.
Int. J. Appl. Math. Comput. Sci., 2018
2016
2015
Proceedings of the Computational Intelligence and Efficiency in Engineering Systems, 2015
Comput. Aided Civ. Infrastructure Eng., 2015
2014
Proceedings of the Progress in Systems Engineering, 2014
Proceedings of the Progress in Systems Engineering, 2014
2013
Proceedings of the Computer Aided Systems Theory - EUROCAST 2013, 2013
Proceedings of the Computer Aided Systems Theory - EUROCAST 2013, 2013
2011
Int. J. Appl. Math. Comput. Sci., 2011
Proceedings of the 21st International Conference on Systems Engineering (ICSEng 2011), 2011
Proceedings of the 21st International Conference on Systems Engineering (ICSEng 2011), 2011
A Tool for Trading-Off On-Line Error Detection Efficiency with Implementation Cost for Sequential Logic Implemented in FPGAs.
Proceedings of the 21st International Conference on Systems Engineering (ICSEng 2011), 2011
Proceedings of the Computer Aided Systems Theory - EUROCAST 2011, 2011
Proceedings of the Computer Aided Systems Theory - EUROCAST 2011, 2011
Trading-Off Error Detection Efficiency with Implementation Cost for Sequential Circuits Implemented with FPGAs.
Proceedings of the Computer Aided Systems Theory - EUROCAST 2011, 2011
2009
Proceedings of the Computer Aided Systems Theory, 2009
Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
2007
Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGAs.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007