Gregor Sievers
According to our database1,
Gregor Sievers
authored at least 10 papers
between 2010 and 2018.
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Collaborative distances:
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2018
CoreVA-MPSoC: A Many-Core Architecture with Tightly Coupled Shared and Local Data Memories.
IEEE Trans. Parallel Distributed Syst., 2018
2016
PhD thesis, 2016
Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation, 2016
2015
Proceedings of the 8th International Workshop on Network on Chip Architectures, 2015
Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOI.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
A communication model and partitioning algorithm for streaming applications for an embedded MPSoC.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014
2013
Design-space exploration of the configurable 32 bit VLIW processor CoreVA for signal processing applications.
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013
2010
Proceedings of the Fifth International Conference on Networking, Architecture, and Storage, 2010