Gregg Baeckler

According to our database, Gregg Baeckler authored at least 13 papers between 2004 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2020

SpiderWeb - High Performance FPGA NoC.

Martin Langhammer, Gregg Baeckler, Sergey Gribok

Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

High Density Pipelined 8bit Multiplier Systolic Arrays for FPGA.

Martin Langhammer, Sergey Gribok, Gregg Baeckler

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

High Density 8-Bit Multiplier Systolic Arrays For Fpga.

Martin Langhammer, Sergey Gribok, Gregg Baeckler

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019

High Performance Scalable FPGA Accelerator for Deep Neural Networks.

Sudarshan Srinivasan, Pradeep Janedula, Saurabh Dhoble, Sasikanth Avancha, Dipankar Das, Naveen Mellempudi, Bharat Daga, Martin Langhammer, Gregg Baeckler, Bharat Kaul

CoRR, 2019

Extracting INT8 Multipliers from INT18 Multipliers.

Martin Langhammer, Bogdan Pasca, Gregg Baeckler, Sergey Gribok

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Fractal Synthesis: Invited Tutorial.

Martin Langhammer, Gregg Baeckler, Sergey Gribok

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

High Precision, High Performance FPGA Adders.

Martin Langhammer, Bogdan Pasca, Gregg Baeckler

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018

High Density and Performance Multiplication for FPGA.

Martin Langhammer, Gregg Baeckler

Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018

2016

HyperPipelining of High-Speed Interface Logic.

Gregg Baeckler

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2006

A methodology for FPGA to structured-ASIC synthesis and verification.

Michael D. Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Efficient SAT-based Boolean matching for FPGA technology mapping.

Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan

Proceedings of the 43rd Design Automation Conference, 2006

2005

The Stratix II logic and routing architecture.

David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004

Improving FPGA Performance and Area Using an Adaptive Logic Module.

Michael D. Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini

Proceedings of the Field Programmable Logic and Application, 2004