Greg Taylor

Orcid: 0000-0001-6495-7731

According to our database1, Greg Taylor authored at least 26 papers between 2004 and 2024.

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Bibliography

2024
A Bifrost Accelerated Intermittent Small Baseline Subset Analysis Pipeline for InSAR Ground Deformation.
Remote. Sens., July, 2024

2023
Lightning Interferometry with the Long Wavelength Array.
Remote. Sens., July, 2023

Cyber Insurance Risk: Reporting Delays, Third-Party Cyber Events, and Changes in Reporting Propensity - An Analysis Using Data Breaches Published by U.S. State Attorneys General.
CoRR, 2023

Machine Learning with High-Cardinality Categorical Features in Actuarial Applications.
CoRR, 2023

2022
Model error and its estimation, with particular application to loss reserving.
CoRR, 2022

BioThings SDK: a toolkit for building high-performance data APIs in biomedical research.
Bioinform., 2022

2021
Modelling and understanding count processes through a Markov-modulated non-homogeneous Poisson process framework.
Eur. J. Oper. Res., 2021

2019
A 1-2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation.
IEEE J. Solid State Circuits, 2019

High Capacity On-Package Physical Link Considerations.
Proceedings of the 2019 IEEE Symposium on High-Performance Interconnects, 2019

2018
Information-Seeking Strategies in Medicine Queries: A Clinical Eye-Tracking Study with Gaze-Cued Retrospective Think-Aloud Protocol.
Int. J. Hum. Comput. Interact., 2018

2015
When the Winning Move is Not to Play: Games of Deterrence in Cyber Security.
Proceedings of the Decision and Game Theory for Security - 6th International Conference, 2015

2013
Re: Search.
New Media Soc., 2013

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A novel digital loop filter architecture for bang-bang ADPLL.
Proceedings of the IEEE 25th International SOC Conference, 2012

Modeling the response of Bang-Bang digital PLLs to phase error perturbations.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2010
HVM performance validation and DFM techniques used in a 32nm CMOS thermal sensor system.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A 1.05 V 1.6 mW, 0.45°C 3σ Resolution ΣΔ Based Temperature Sensor With Parasitic Resistance Compensation in 32 nm Digital CMOS Process.
IEEE J. Solid State Circuits, 2009

A 1.05V 1.6mW 0.45°C 3σ-resolution ΔΣ-based temperature sensor with parasitic-resistance compensation in 32nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction.
IEEE J. Solid State Circuits, 2008

2007
On-Die Supply-Resonance Suppression Using Band-Limited Active Damping.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Enhancing microprocessor immunity to power supply noise with clock-data compensation.
IEEE J. Solid State Circuits, 2006

2004
On-die droop detector for analog sensing of power supply noise.
IEEE J. Solid State Circuits, 2004

I/O Self-Leakage Test.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004


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