Greg Sadowski

According to our database, Greg Sadowski authored at least 7 papers between 2013 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2021

Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems.

Davide Bertozzi, Gabriele Miorandi, Alberto Ghiribaldi, Wayne P. Burleson, Greg Sadowski, Kshitij Bhardwaj, Weiwei Jiang, Steven M. Nowick

IEEE Micro, 2021

2018

Case Study of Process Variation-Based Domain Partitioning of GPGPUs.

Shomit Das, Michael LeBeane, Bradford M. Beckmann, Greg Sadowski

Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018

2017

Design and Analysis of an APU for Exascale Computing.

Thiruvengadam Vijayaraghavan, Yasuko Eckert, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Bradford M. Beckmann, William C. Brantley, Joseph L. Greathouse, Wei Huang, Arun Karunanithi, Onur Kayiran, Mitesh R. Meswani, Indrani Paul, Matthew Poremba, Steven Raasch, Steven K. Reinhardt, Greg Sadowski, Vilas Sridharan

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart.

Weiwei Jiang, Davide Bertozzi, Gabriele Miorandi, Steven M. Nowick, Wayne P. Burleson, Greg Sadowski

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Reconfigurable Links for Self-Timed On-Chip Communication.

Shomit Das, Greg Sadowski

Proceedings of the 9th International Workshop on Network on Chip Architectures, 2016

2014

Design and implementation of novel source synchronous interconnection in modern GPU chips.

Tao Li, Greg Sadowski

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

2013

Low-power Networks-on-Chip: Progress and remaining challenges.

Mark Buckler, Wayne P. Burleson, Greg Sadowski

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013