Graham Hetherington

According to our database, Graham Hetherington authored at least 7 papers between 1990 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2005

Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems.

Iain Robertson, Graham Hetherington, Tom Leslie, Ishwar Parulkar, Ronald Lesnikoski

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004

A Holistic Parallel and Hierarchical Approach towards Design-For-Test.

C. P. Ravikumar, Graham Hetherington

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques.

Kenneth M. Butler, Jayashree Saxena, Tony Fryars, Graham Hetherington

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

Circular BIST testing the digital logic within a high speed Serdes.

Graham Hetherington, Richard Simpson

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

1999

Logic BIST for large industrial designs: real issues and case studies.

Graham Hetherington, Tony Fryars, Nagesh Tamarapalli, Mark Kassab, Abu S. M. Hassan, Janusz Rajski

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1995

Test Generation and Design for Test for a Large Multiprocessing DSP.

Graham Hetherington, Greg Sutton, Kenneth M. Butler, Theo J. Powell

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1990

High-Level Synthesis: Technology Transfer to Industry.

Robin C. Sarma, Mark D. Dooley, N. Craig Newman, Graham Hetherington

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990