Gracieli Posser

According to our database, Gracieli Posser authored at least 20 papers between 2010 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

Introduction to the Special Section on Advances in Physical Design Automation.

Iris Hui-Ru Jiang, David G. Chinnery, Gracieli Posser, Jens Lienig

ACM Trans. Design Autom. Electr. Syst., September, 2023

2022

Challenges and Approaches in VLSI Routing.

Gracieli Posser, Evangeline F. Y. Young, Stephan Held, Yih-Lang Li, David Z. Pan

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2019

ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules.

Wen-Hao Liu, Stefanus Mantik, Wing-Kai Chow, Yixiao Ding, Amin Farshidi, Gracieli Posser

Proceedings of the 2019 International Symposium on Physical Design, 2019

2018

ISPD 2018 Initial Detailed Routing Contest and Benchmarks.

Stefanus Mantik, Gracieli Posser, Wing-Kai Chow, Yixiao Ding, Wen-Hao Liu

Proceedings of the 2018 International Symposium on Physical Design, 2018

2016

Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization.

Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Reducing the number of transistors with gate clustering.

Calebe Conceição, Gracieli Posser, Ricardo Reis

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

FinFET cells with different transistor sizing techniques against PVT variations.

Alexandra L. Zimpeck, Cristina Meinhardt, Gracieli Posser, Ricardo Augusto da Luz Reis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Electromigration aware circuits by using special signal non-default routing rules.

Lucas de Paris, Gracieli Posser, Ricardo Reis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

Reducing the signal Electromigration effects on different logic gates by cell layout optimization.

Gracieli Posser, Lucas de Paris, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar

Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Process variability in FinFET standard cells with different transistor sizing techniques.

Alexandra L. Zimpeck, Cristina Meinhardt, Gracieli Posser, Ricardo Reis

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Impact on performance, power, area and wirelength using electromigration-aware cells.

Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014

Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation.

Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices.

Gracieli Posser, Jozeanne Belomo, Cristina Meinhardt, Ricardo Augusto da Luz Reis

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Analyzing the electromigration effects on different metal layers and different wire lengths.

Gracieli Posser, Vivek Mishra, Ricardo Augusto da Luz Reis, Sachin S. Sapatnekar

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

A systematic approach for analyzing and optimizing cell-internal signal electromigration.

Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013

Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities.

Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing.

Tiago Reimann, Gracieli Posser, Guilherme Flach, Marcelo O. Johann, Ricardo Reis

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

Transistor sizing and gate sizing using geometric programming considering delay minimization.

Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

2011

Gate Sizing Minimizing Delay and Area.

Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010

A study on layout quality of automatic generated cells.

Gracieli Posser, Adriel Ziesemer, Daniel Guimares Jr., Gustavo Wilke, Ricardo A. L. Reis

Proceedings of the 17th IEEE International Conference on Electronics, 2010