Govind Prasad

Orcid: 0000-0002-3163-9451

According to our database1, Govind Prasad authored at least 8 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2024
SEDONUT: A Single Event Double Node Upset Tolerant SRAM for Terrestrial Applications.
ACM Trans. Design Autom. Electr. Syst., May, 2024

Design of an SRAM-bitcell with enhanced self-recoverability from soft errors for space and critical terrestrial applications.
Integr., 2024

2022
Energy-efficient radiation hardened SRAM cell for low voltage terrestrial applications.
Microelectron. J., 2022

Novel low-power and stable memory cell design using hybrid CMOS and MTJ.
Int. J. Circuit Theory Appl., 2022

2020
Power optimized SRAM cell with high radiation hardened for aerospace applications.
Microelectron. J., 2020

Design and statistical analysis of low power and high speed 10T static random access memory cell.
Int. J. Circuit Theory Appl., 2020

2019
Design and Analysis of 10T-Boosted Radiation Hardened SRAM Cell for Aerospace Applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

2016
Design and analysis of phase locked loop in 90nm CMOS.
Proceedings of the Thirteenth International Conference on Wireless and Optical Communications Networks, 2016


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