Goro Kitsukawa

According to our database, Goro Kitsukawa authored at least 5 papers between 1989 and 1996.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1996

A 29-ns 64-Mb DRAM with hierarchical array architecture.

Masayuki Nakamura, Tugio Takahashi, Takesada Akiba, Goro Kitsukawa, Makoto Morino, Toshihiro Sekiguchi, Isamu Asano, Katsuo Komatsuzaki, Yoshitaka Tadaki, Songsu Cho, Kazuhiko Kajigaya, Tadashi Tachibana, Katsuyuki Sato

IEEE J. Solid State Circuits, 1996

1994

A charge recycle refresh for Gb-scale DRAM's in file applications.

Takayulu Kawahara, Yoshiki Kawajiri, Masashi Horiguchi, Takesada Akiba, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki

IEEE J. Solid State Circuits, June, 1994

1989

Substrate current reduction techniques for BiCMOS DRAM.

Takayuki Kawahara, Goro Kitsukawa, Hisayuki Higuchi, Yoshiki Kawajiri, Takao Watanabe, Kiyoo Itoh, Ryoichi Hori, Yutaka Kobayashi, Tetsuro Matsumoto

IEEE J. Solid State Circuits, October, 1989

Comparison of CMOS and BiCMOS 1-Mbit DRAM performance.

Takao Watanabe, Goro Kitsukawa, Yoshiki Kawajiri, Kiyoo Itoh, Ryoichi Hori, Yoshiaki Ouchi, Takayuki Kawahara, Tetsuro Matsumoto

IEEE J. Solid State Circuits, June, 1989

A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques.

Goro Kitsukawa, Kiyoo Itoh, Ryoichi Hori, Yoshiki Kawajiri, Takao Watanabe, Takayuki Kawahara, Tetsuro Matsumoto, Yutaka Kobayashi

IEEE J. Solid State Circuits, June, 1989