Goro Kitsukawa

According to our database, Goro Kitsukawa authored at least 11 papers between 1989 and 1996.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1996

A 29-ns 64-Mb DRAM with hierarchical array architecture.

Masayuki Nakamura, Tugio Takahashi, Takesada Akiba, Goro Kitsukawa, Makoto Morino, Toshihiro Sekiguchi, Isamu Asano, Katsuo Komatsuzaki, Yoshitaka Tadaki, Songsu Cho, Kazuhiko Kajigaya, Tadashi Tachibana, Katsuyuki Sato

IEEE J. Solid State Circuits, 1996

1994

A charge recycle refresh for Gb-scale DRAM's in file applications.

Takayulu Kawahara, Yoshiki Kawajiri, Masashi Horiguchi, Takesada Akiba, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki

IEEE J. Solid State Circuits, June, 1994

1993

256-Mb DRAM circuit technologies for file applications.

Goro Kitsukawa, Masashi Horiguchi, Yoshiki Kawajiri, Takayuki Kawahara, Takesada Akiba, Yasushi Kawase, Toshikazu Tachibana, Takeshi Sakai, Masakazu Aoki, Syoji Shukuri, Kazuhiko Sagara, Ryo Nagai, Yuzuru Ohji, Nono Hasegawa, Natsuki Yokoyama, Teruaki Kisu, Hisaomi Yamashita, Tokuo Kure, Takashi Nishida

IEEE J. Solid State Circuits, November, 1993

Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs).

Takayuki Kawahara, Masashi Horiguchi, Yoshiki Kawajiri, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki

IEEE J. Solid State Circuits, November, 1993

A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays.

Takayuki Kawahara, Takeshi Sakata, Kiyoo Itoh, Yoshiki Kawajiri, Takesada Akiba, Goro Kitsukawa, Masakazu Aoki

IEEE J. Solid State Circuits, July, 1993

1992

Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-Mb DRAM's.

Takayuki Kawahara, Yoshiki Kawajiri, Goro Kitsukawa, Kazuhiko Sagara, Yoshifumi Kawamoto, Takesada Akiba, Shisei Kato, Yasushi Kawase, Kiyoo Itoh

IEEE J. Solid State Circuits, April, 1992

1991

A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's.

Takayuki Kawahara, Yoshiki Kawajiri, Goro Kitsukawa, Yoshinobu Nakagome, Kazuhiko Sagara, Yoshifumi Kawamoto, Takesada Akiba, Shisei Kato, Yasushi Kawase, Kiyoo Itoh

IEEE J. Solid State Circuits, November, 1991

1990

A 23-ns 1-Mb BiCMOS DRAM.

Goro Kitsukawa, Kazumasa Yanagisawa, Yutaka Kobayashi, Yoshitaka Kinoshita, Tatsuyuki Ohta, Tetsu Udagawa, Hitoshi Miwa, Hiroyuki Miyazawa, Yoshiki Kawajiri, Yoshiaki Ouchi, Hiromi Tsukada, Tetsuro Matsumoto, Kiyoo Itoh

IEEE J. Solid State Circuits, October, 1990

1989

Substrate current reduction techniques for BiCMOS DRAM.

Takayuki Kawahara, Goro Kitsukawa, Hisayuki Higuchi, Yoshiki Kawajiri, Takao Watanabe, Kiyoo Itoh, Ryoichi Hori, Yutaka Kobayashi, Tetsuro Matsumoto

IEEE J. Solid State Circuits, October, 1989

Comparison of CMOS and BiCMOS 1-Mbit DRAM performance.

Takao Watanabe, Goro Kitsukawa, Yoshiki Kawajiri, Kiyoo Itoh, Ryoichi Hori, Yoshiaki Ouchi, Takayuki Kawahara, Tetsuro Matsumoto

IEEE J. Solid State Circuits, June, 1989

A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques.

Goro Kitsukawa, Kiyoo Itoh, Ryoichi Hori, Yoshiki Kawajiri, Takao Watanabe, Takayuki Kawahara, Tetsuro Matsumoto, Yutaka Kobayashi

IEEE J. Solid State Circuits, June, 1989