Gordon Russell

Affiliations:
  • Newcastle University, School of Electrical, Electronic and Computer Engineering, Newcastle upon Tyne, United Kingdom


According to our database1, Gordon Russell authored at least 24 papers between 2002 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2012
Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural Level.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Statistical delay modelling of manufacturing process variations at system level.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

VARMA - VARiability modelling and analysis tool.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Reconfigurable time interval measurement circuit incorporating a programmable gain time difference amplifier.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Sub-threshold synchronizer.
Microelectron. J., 2011

Design and analysis of a low-swing driver scheme for long interconnects.
Microelectron. J., 2011

M-PRES: a statistical tool for modelling the impact of manufacturing process variations on circuit-level performance parameters.
IET Circuits Devices Syst., 2011

2010
Extending Synchronization from Super-Threshold to Sub-threshold Region.
Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems, 2010

2008
On-Chip Measurement of Deep Metastability in Synchronizers.
IEEE J. Solid State Circuits, 2008

Statistical modelling of the variation in advanced process technologies using a multi-level partitioned response.
IET Circuits Devices Syst., 2008

The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk.
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

High resolution flash time-to-digital converter with sub-picosecond measurement capabilities.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

Adapting Synchronizers to the Effects of on Chip Variability.
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008

FPGA Implementation of an Asynchronous Processor with Both Online and Offline Testing Capabilities.
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008

2007
Measuring Deep Metastability and Its Effect on Synchronizer Performance.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Built-in time measurement circuits - a comparative design study.
IET Comput. Digit. Tech., 2007

Embedded high-resolution delay measurement system using time amplification.
IET Comput. Digit. Tech., 2007

A Low Power Information Redundant Concurrent Error Detecting Asynchronous Processor.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007

2006
A Robust Synchronizer.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Measuring Deep Metastability.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

2004
Design of Sub-10-Picoseconds On-Chip Time Measurement Circuit.
Proceedings of the 2004 Design, 2004

2003
On-chip structures for timing measurement and test.
Microprocess. Microsystems, 2003

2002
On-Chip Structures for Timing Measurements and Test.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002


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