Gopalkrishna Nayak
According to our database1,
Gopalkrishna Nayak
authored at least 5 papers
between 2009 and 2018.
Collaborative distances:
Collaborative distances:
Timeline
2009
2010
2011
2012
2013
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2018
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2018
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
2016
A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
2011
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011
2009
A 65nm CMOS, ring-oscillator based, high accuracy Digital Phase Lock Loop for USB2.0.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009