Gong Chen

According to our database, Gong Chen authored at least 12 papers between 2012 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Routable and Matched Layout Styles for Analog Module Generation.

Bo Liu, Gong Chen, Bo Yang, Shigetoshi Nakatake

ACM Trans. Design Autom. Electr. Syst., 2018

2016

DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout.

Gong Chen, Toru Fujimura, Qing Dong, Shigetoshi Nakatake, Bo Yang

ACM Trans. Design Autom. Electr. Syst., 2016

A multi-functional memory unit with PLA-based reconfigurable decoder.

Nobuyuki Yahiro, Bo Liu, Atsushi Nanri, Shigetoshi Nakatake, Yasuhiro Takashima, Gong Chen

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Routability of twisted common-centroid capacitor array under signal coupling constraints.

Gong Chen, Bo Liu, Shigetoshi Nakatake, Bo Yang

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Twin-row-style for MOS analog layout.

Bo Liu, Shigetoshi Nakatake, Bo Yang, Gong Chen

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015

Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC.

Gong Chen, Yu Zhang, Qing Dong, Mingyu Li, Shigetoshi Nakatake

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

2013

Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming.

Yu Zhang, Gong Chen, Bo Yang, Jing Li, Qing Dong, Mingyu Li, Shigetoshi Nakatake

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects.

Yu Zhang, Gong Chen, Qing Dong, Mingyu Li, Shigetoshi Nakatake

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

A comparator energy model considering shallow trench isolation stress by geometric programming.

Gong Chen, Yu Zhang, Bo Yang, Qing Dong, Shigetoshi Nakatake

Proceedings of the International Symposium on Quality Electronic Design, 2013

A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm.

Gong Chen, Bo Yang, Yu Zhang, Qing Dong, Shigetoshi Nakatake

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

Transistor channel decomposition for structured analog layout, manufacturability and low-power applications.

Qing Dong, Bo Yang, Gong Chen, Jing Li, Shigetoshi Nakatake

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model.

Gong Chen, Bo Yang, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012